HT46R64 Holtek Semiconductor Inc., HT46R64 Datasheet - Page 13

• Manufacturer Part Number: HT46R64
• Description: Ht46r64/ht46c64 -- A/d With Lcd Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

There is another oscillator circuit designed for the real
time clock. In this case, only the 32.768kHz crystal oscil-
lator can be applied. The crystal should be connected
between OSC3 and OSC4.
The RTC oscillator circuit can be controlled to oscillate
quickly by setting the QOSC bit (bit 4 of RTCC). It is
recommended to turn on the quick oscillating function
upon power on, and then turn it off after 2 seconds.
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Although
the system enters the power down mode, the system
clock stops, and the WDT oscillator still works with a pe-
riod of approximately 65 s at 5V. The WDT oscillator
can be disabled by options to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC os-
cillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled, all exe-
cutions related to the WDT lead to no operation.
Once an internal WDT oscillator (RC oscillator with pe-
riod 65 s at 5V normally) is selected, it is divided by
2
minimum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with tem-
perature, VDD and process variations. By selection the
WDT option, longer time-out periods can be realized. If
the WDT time-out is selected 2
period is divided by 2
oscillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the halt state the WDT may stop counting
and lose its protecting purpose. In this situation the logic
can only be restarted by external logic. If the device op-
erates in a noisy environment, using the on-chip RC os-
cillator (WDT OSC) is strongly recommended, since the
HALT will stop the system clock.
Rev. 1.80
12
~2
15
(by option to get the WDT time-out period). The
15
~2
16
about 2.1s~4.3s. If the WDT
15
, the maximum time-out
Watchdog Timer
13
The WDT overflow under normal operation initializes a
mode, the overflow initializes a warm reset , and only
the program counter and SP are reset to zero. To clear
the contents of the WDT, there are three methods to be
adopted, i.e., external reset (a low level to RES), soft-
ware instruction, and a HALT instruction. There are
two types of software instructions; CLR WDT and the
other set
two types of instruction, only one type of instruction can
be active at a time depending on the options
WDT times selection option. If the CLR WDT is se-
lected (i.e., CLR WDT times equal one), any execution
of the CLR WDT instruction clears the WDT. In the
case that CLR WDT1 and CLR WDT2 are chosen
(i.e., CLR WDT times equal two), these two instructions
have to be executed to clear the WDT; otherwise, the
WDT may reset the chip due to time-out.
Multi-function Timer
The HT46R64/HT46C64 provides a multi-function timer
for the WDT, time base and RTC but with different
time-out periods. The multi-function timer consists of an
8-stage divider and a 7-bit prescaler, with the clock
source coming from the WDT OSC or RTC OSC or the
instruction clock (i.e., system clock divided by 4). The
multi-function timer also provides a selectable fre-
quency signal (ranges from f
circuits, and a selectable frequency signal (ranging from
f
ommended to select a nearly 4kHz signal for the LCD
driver circuits to have proper display.
Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from 2
base time-out occurs, the related interrupt request flag
(TBF; bit 5 of INTC1) is set. But if the interrupt is en-
abled, and the stack is not full, a subroutine call to loca-
tion 14H occurs.
S
chip reset and sets the status bit TO . In the HALT
/2
2
to f
S
/2
9
) for the buzzer output by options. It is rec-
CLR WDT1 and CLR WDT2 . Of these
12
/f
S
to 2
15
/f
HT46R64/HT46C64
S
selected by options. If time
S
/2
2
to f
S
February 14, 2006
/2
8
) for LCD driver
CLR