DSPIC30F4013 Microchip Technology Inc., DSPIC30F4013 Datasheet - Page 215

• Manufacturer Part Number: DSPIC30F4013
• Description: Dspic30f3014/4013 High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

T
Table Instruction Operation Summary ................................ 41
Temperature and Voltage Specifications
Timer1 Module .................................................................... 63
Timer2 and Timer3 Selection Mode .................................... 81
Timer2/3 Module ................................................................. 67
Timer4/5 Module ................................................................. 73
Timing Characteristics
Timing Diagrams
© 2007 Microchip Technology Inc.
AC ............................................................................. 174
DC............................................................................. 165
16-bit Asynchronous Counter Mode ........................... 63
16-bit Synchronous Counter Mode ............................. 63
16-bit Timer Mode....................................................... 63
Gate Operation ........................................................... 64
Interrupt....................................................................... 64
Operation During Sleep Mode .................................... 64
Prescaler..................................................................... 64
Real-Time Clock ......................................................... 64
Register Map............................................................... 66
16-bit Timer Mode....................................................... 67
32-bit Synchronous Counter Mode ............................. 67
32-bit Timer Mode....................................................... 67
ADC Event Trigger...................................................... 70
Gate Operation ........................................................... 70
Interrupt....................................................................... 70
Operation During Sleep Mode .................................... 70
Register Map............................................................... 71
Timer Prescaler........................................................... 70
Register Map............................................................... 75
A/D Conversion
Bandgap Start-up Time............................................. 180
CAN Module I/O........................................................ 198
CLKO and I/O ........................................................... 178
DCI Module
External Clock........................................................... 174
I
I
Input Capture (CAPX) ............................................... 183
OC/PWM Module ...................................................... 184
Oscillator Start-up Timer ........................................... 179
Output Compare Module........................................... 183
Power-up Timer ........................................................ 179
Reset......................................................................... 179
SPI Module
Type A, B and C Timer External Clock ..................... 181
Watchdog Timer........................................................ 179
CAN Bit ..................................................................... 110
Frame Sync, AC-Link Start-of-Frame ....................... 118
Frame Sync, Multichannel Mode .............................. 118
I
PWM Output ............................................................... 83
2
2
2
C Bus Data
C Bus Start/Stop Bits
S Interface Frame Sync.......................................... 118
Interrupts............................................................. 65
Oscillator Operation ............................................ 65
Low-speed (ASAM = 0, SSRC = 000) .............. 201
AC-Link Mode ................................................... 187
Multichannel, I
Master Mode ..................................................... 194
Slave Mode ....................................................... 196
Master Mode ..................................................... 194
Slave Mode ....................................................... 196
Master Mode (CKE = 0) .................................... 189
Master Mode (CKE = 1) .................................... 190
Slave Mode (CKE = 0) ...................................... 191
Slave Mode (CKE = 1) ...................................... 192
2
S Modes ................................... 185
Timing Diagrams and Specifications
Timing Diagrams.See Timing Characteristics
Timing Requirements
Trap Vectors ....................................................................... 59
U
UART Module
dsPIC30F3014/4013
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR Tied
DC Characteristics - Internal RC Accuracy .............. 176
A/D Conversion
Bandgap Start-up Time ............................................ 180
Brown-out Reset....................................................... 180
CAN Module I/O ....................................................... 198
CLKO and I/O ........................................................... 178
DCI Module
External Clock .......................................................... 175
I
I
Input Capture............................................................ 183
Oscillator Start-up Timer........................................... 180
Output Compare Module .......................................... 183
Power-up Timer ........................................................ 180
Reset ........................................................................ 180
Simple OC/PWM Mode ............................................ 184
SPI Module
Type A Timer External Clock .................................... 181
Type B Timer External Clock .................................... 182
Type C Timer External Clock.................................... 182
Watchdog Timer ....................................................... 180
Address Detect Mode ............................................... 101
Auto Baud Support ................................................... 102
Baud Rate Generator ............................................... 101
Enabling and Setting Up............................................. 99
Framing Error (FERR) .............................................. 101
Idle Status................................................................. 101
Loopback Mode ........................................................ 101
Operation During CPU Sleep and Idle Modes.......... 102
Overview..................................................................... 97
Parity Error (PERR) .................................................. 101
Receive Break .......................................................... 101
Receive Buffer (UxRXB)........................................... 100
Receive Buffer Overrun Error (OERR Bit) ................ 100
Receive Interrupt ...................................................... 100
Receiving Data ......................................................... 100
Receiving in 8-bit or 9-bit Data Mode ....................... 100
Reception Error Handling ......................................... 100
Transmit Break ......................................................... 100
Transmit Buffer (UxTXB) ............................................ 99
Transmit Interrupt ..................................................... 100
Transmitting Data ....................................................... 99
Transmitting in 8-Bit Data Mode ................................. 99
Transmitting in 9-bit Data Mode ................................. 99
UART1 Register Map ............................................... 103
UART2 Register Map ............................................... 103
2
2
C Bus Data (Master Mode) .................................... 194
C Bus Data (Slave Mode) ...................................... 197
Not Tied to V
Not Tied to V
to V
Low-speed ........................................................ 202
AC-Link Mode................................................... 188
Multichannel, I
Master Mode (CKE = 0).................................... 189
Master Mode (CKE = 1).................................... 190
Slave Mode (CKE = 0)...................................... 191
Slave Mode (CKE = 1)...................................... 193
DD
).............................................................. 146
DD
DD
2
S Modes................................... 185
), Case 1.................................. 146
), Case 2.................................. 146
DS70138E-page 213