DSPIC30F4013 Microchip Technology Inc., DSPIC30F4013 Datasheet - Page 62

• Manufacturer Part Number: DSPIC30F4013
• Description: Dspic30f3014/4013 High-performance, 16-bit Digital Signal Controllers
• Manufacturer: Microchip Technology Inc.

dsPIC30F3014/4013
8.6
A context saving option is available using shadow reg-
isters. Shadow registers are provided for the DC, N,
OV, Z and C bits in SR, and the registers W0 through
W3. The shadows are only one level deep. The shadow
registers are accessible using the PUSH.S and POP.S
instructions only.
When the processor vectors to an interrupt, the
PUSH.S instruction can be used to store the current
value of the aforementioned registers into their
respective shadow registers.
If an ISR of a certain priority uses the PUSH.S and
POP.S instructions for fast context saving, then a
higher priority ISR should not include the same instruc-
tions. Users must save the key registers in software
during a lower priority interrupt if the higher priority ISR
uses fast context saving.
DS70138E-page 60
Fast Context Saving
8.7
The interrupt controller supports up to five external
interrupt request signals, INT0-INT4. These inputs are
edge sensitive; they require a low-to-high or a high-to-
low transition to generate an interrupt request. The
INTCON2 register has three bits, INT0EP-INT2EP, that
select the polarity of the edge detection circuitry.
8.8
The interrupt controller may be used to wake-up the
processor from either Sleep or Idle modes, if Sleep or
Idle mode is active when the interrupt is generated.
If an enabled interrupt request of sufficient priority is
received by the interrupt controller, then the standard
interrupt request is presented to the processor. At the
same time, the processor wakes up from Sleep or Idle
and begins execution of the Interrupt Service Routine
(ISR) needed to process the interrupt request.
External Interrupt Requests
Wake-up from Sleep and Idle
© 2007 Microchip Technology Inc.