DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet - Page 46

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DSP56721

Manufacturer Part Number
DSP56721
Description
Dsp56721 Multi-core Audio Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
46
LCLK cycle time
Input setup to LCLK (except LGTA/LUPWAIT)
Input hold from LCLK (except LGTA/LUPWAIT)
LGTA valid time
LUPWAIT valid time
LALE negedge to LAD (address phase) invalid (address
latch hold time)
LALE valid time
Output setup from LCLK (except LAD[23:0] and LALE)
Output hold from LCLK (except LAD[23:0] and LALE)
LA[2:0]/LBCTL/LCS[7:0]
LOE/LWE
LSDWE/LSDRAS/LSDCAS
LGPL[5:0]
LCKE/LSDA10/LSDDQM
Output Signals
Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
LAD[23:0] (data)
Symphony
Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4)
LUPWAIT
LAD[23:0]
Parameter
LGTA
LALE
LCLK
TM
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3
asynchronous input
asynchronous input
1
T
T
ad_s
out_s
T
ale
Symbol
T
T
T
T
T
T
T
T
ad_h
upwait
T
out_h
T
T
out_h
ale_h
out_s
T
in_s
in_h
gta
ale
clk
T
upwait
ale_h
T
T
T
ad_z
gta
in_s
T
in_h
T
clk
Min
40
42
42
34
19
18
-1
8
5
Max
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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