DSP56721 Freescale Semiconductor, Inc, DSP56721 Datasheet - Page 47

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DSP56721

Manufacturer Part Number
DSP56721
Description
Dsp56721 Multi-core Audio Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Freescale Semiconductor
LAD[23:0] output setup from LCLK
LAD[23:0] output hold from LCLK
LCLK to output high impedance for LAD[23:0]
Notes:
1. A negative hold time means that the signal could be invalid before the LCLK rising edge.
Table 22. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8) (Continued)
LA[2:0]/LBCTL/LCS[7:0]
LOE/LWE
LSDWE/LSDRAS/LSDCAS
LGPL[5:0]
LCKE/LSDA10/LSDDQM
Output Signals
LAD[23:0] (data)
Symphony
Figure 40. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 8)
LUPWAIT
LAD[23:0]
Parameter
LGTA
LCLK
LALE
TM
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev. 3
asynchronous input
asynchronous input
T
T
ad_s
out_s
T
ale
Symbol
T
T
T
T
T
ad_s
ad_h
ad_z
ad_h
out_h
T
T
upwait
ale_h
T
T
T
ad_z
gta
in_s
T
in_h
T
clk
Min
18
17
Max
19
Unit
ns
ns
ns
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