HN29V1G91T-30 Renesas Electronics Corporation., HN29V1G91T-30 Datasheet

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... HN29V1G91T-30 128M × 8-bit AG-AND Flash Memory Description The HN29V1G91 series achieves a write speed of 10 Mbytes/sec, which is 5 times faster than Renesas's previous multi level cell Flash memory, using 0.13µm process technology and AG-AND (Assist Gate- AND) type Flash memory cell using multi level cell technology provides both the most cost effective solution and high speed programming ...

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... Erase cycles to one block. You should adopt wear leveling once in 5000 Program and Erase cycles better to program variable by software. 5 • Program/Erase Endurance: 10 cycles • Package line up  TSOP: TSOP Type-I 48pin package (TFP-48DA) Ordering Information Type No. Operating voltage (V HN29V1G91T-30 2 3.6 V Rev.4.00, Jun.20.2004, page Organization Package CC ×8 12.0 × 20.00 mm 0.5 mm pitch ...

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... HN29V1G91T-30 Pin Arrangement 4 R CLE 16 ALE Pin configuration Pin name Function I I/O 8 Command, address, data Input/output CLE Command Latch Enable ...

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... HN29V1G91T-30 Block Diagram 16 Page address buffer 16 I/ Data Multi- to input plexer buffer I/O8 Input data V CC control Column address counter R/* Read/Program/Erase +- control 4- Control 9- signal buffer 92 CLE ALE PRE 4-5 Rev.4.00, Jun.20.2004, page Bank0 Bank Bank 1 2 Memory array X- (2048+64) decoder ...

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... HN29V1G91T-30 Memory map and address Memory Map FFFFH FFFEH FFFDH 0006H 0005H 0004H 0003H 0002H 0001H 2048bytes 0000H Data register 2048bytes Bank Organization Bank0 (8192Blocks) (16384pages) Block 0 page 0 page 4 Block 4 page 8 page 12 Block 32764 page 65528 page 65532 Addressing Symbol I/O8 1st Cycle ...

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... HN29V1G91T-30 Pin Functions Chip Enable used for the selection of the device. It goes to the standby mode when +- goes to ‘H’ level when the device is in the Output disable state. When the device is in the Busy state during Program or Erase or Read operation, +- signal is ignored and the device does not return to the standby mode even if +- goes to High ...

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... HN29V1G91T-30 Reset: 4-5 The 4-5 signal controls reset operation for device. When power on and power off, keep pin V (V ± 0.2V), and keep pin V level (V SS IHD The transition to deep standby mode is executed when 4-5 set V Power on auto Read Enable: PRE The PRE controls auto read operation executed during power-on. The power-on auto-read is enabled when PRE pin is tied Please contact Renesas Technology’ ...

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... HN29V1G91T-30 Mode selection The address input, command input, and data input/output operation of the device are controlled by 4-5, 92, 9-, +-, CLE, ALE, 4-, PRE signals. The following shows the operation logic table. Logic Table 4-5* Mode Read Mode Command Input Address Input (4clock) Write Mode Command Input ...

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... HN29V1G91T-30 Command Definition Command Sets Read Multi Bank Read Random Data output in a Page Read for copy back Copy Back Program Page Data output Multi Bank Copy Back Program Data Recovery Read Data Recovery Program Reset Page Program Random Data Input in a Page ...

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... HN29V1G91T-30 Device Operation Page Read It becomes Busy state with 9- rising edge after writing 00h along with four address cycles and 30h and data transfer starts from memory array to the data register. The device output the data serially from specified column address when inputting address by the repetitive high to low transition of the 4- clock after it is Ready state ...

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... HN29V1G91T-30 CLE +- 9- ALE 4- column address M I/O 00h CA1 CA2 R/* Memory array Data register M 4page read R/* pageN column J N=0,4,8,12... I/O 00h CA1 CA2 RA1 RA2 30h (1) R/*(A) columnL pageN+2 I/O (B) 06h CA1 CA2 RA1 RA2 E0h (4) Bank 0 Page N Memory array Data register Bank 0 Page N Memory array ...

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... HN29V1G91T-30 Random Data output in a Page Read When the device output the data serially in Page read mode operation, the data from any column address in a Page which is reading can be output by writing 05h and E0h with two column address cycles. There is no restriction on an order of column address which can be specified and it is possible to specify many times including same column address in the same Page address ...

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... HN29V1G91T-30 Multi Bank Read Multi Bank Read operation enables to read the data of any Page address in 4 bank. Writing 00h command with four address cycles can be specified to maximum 4 Bank. There is no restriction on an order of a Bank to specify. Page address specified later becomes effective when it is specified twice in the same Bank. ...

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... HN29V1G91T-30 Multi Bank Read Random Data output The data can be read out setting column address freely on the way to the read operation of Page address data in each Bank in Multi Bank Read operation possible to read out the data by writing 05h and E0h command with two column address cycles. There is no restriction to specify any column address and it is possible to specify it including same one in the same page address many times ...

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... HN29V1G91T-30 Page Program Page program operation enables to write the data into one Page address. The data is stored into the data register after writing 80h command with four address input (Column address, Page address) and data input also stored serially from column address which is input and then automatic program operation starts after writing 10h command (Program command) ...

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... HN29V1G91T-30 Page Program Random Data input in a Page This operation enables to input the program data in the Page address randomly writing 85h command with two column address input on the way to the program operation in the Page program mode. It can input the data by specifying a column address in the same page which you want to program the data using this mode ...

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... HN29V1G91T-30 Multi Bank Page Program It is possible to program the data to any one page address in each bank simultaneously since this device adopts 4 bank structure. The bank to be programmed the data is chosen from 1 bank to maximum 4 bank. Address and data for next bank can be input consecutively by writing 11h command (dummy command) after writing 80h command with column and page address, data as well as usual page program ...

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... HN29V1G91T-30 Multi Bank Page Program Random Data Input in a Page This mode enables to input program data specifying an address in a page which the data is programmed when Multi Bank Page Program operation. The data can be input serially by writing 85h command with column address to on the way to the data input to the page address to be programmed as well as random data input in page mode ...

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... HN29V1G91T-30 Cache Program Cache program operation enables to use the data register of the bank which do not program as the cache register. The program data for next page address is transferred to Flash memory from external data buffer by using the cache register while programming the primary data. ...

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... HN29V1G91T-30 2page Cache Program 2 page cache program operation is available using both Multi Bank Program and Cache Program operation. It enables to input the program data for the address of next bank consecutively by writing 11h command (dummy command) following 80h command and program address/data input. Setup for program starts by ...

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... HN29V1G91T-30 Copy Back Program Copy Back Program operation enables to copy the data to different page address of same bank without taking it to external data register. The data transfer to the data register is started to copy memory array data of 1 page address writing 35h command following 00h command and address input with 4 cycles. Then copy of the data is started by writing 10h command following 85h command and address with 4 cycles for post-copy ...

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... HN29V1G91T-30 Copy Back Program with Random Data Input In a Page Source copy data which has transferred to the data register can be updated when copy back program operation is executed. Memory array data which has taken out to the data register is updated to the input data after storing source copy data to the data register and inputting the data following 85h command and 4 address input with 4 cycles ...

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... HN29V1G91T-30 Copy Back Program with Data Output When copy back program operation is executed possible to confirm the source copy data outputting one which has transferred to the data register to external possible to output the source copy data after storing it to the data register and inputting E0h command following 06h command and address input with 4 cycles ...

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... HN29V1G91T-30 Copy Back Program with Data Output and Random Data Input in a Page R/* column J page M 00h CA1 CA2 RA1 RA2 I/O (1) (A) R/* column L (B) I/O 85h CA1 CA2 D IN (4) Bank 0 Memory array Page M (1) Data register Bank 0 Memory array Data register column J’ ...

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... HN29V1G91T-30 Multi Bank Copy Back Program Multi Bank Copy Back Program enables to execute copy back program to a multiple bank simultaneously. The data is transferred to the data register from memory array simultaneously by writing 35h command after specifying post copy address consecutively. Data read and update can be executed as well as copy back program ...

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... HN29V1G91T-30 Data Recovery Read Data recovery read enables to output the data itself which is transferred from external after program completion possible to read out the data which is programmed by writing E0h command following 06h command and read address input with 4 cycles also possible to read out the data of any column address in same page address by writing E0h command following 05h command and column address input with 2 cycles on the way to outputting the data by clocking 4- ...

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... HN29V1G91T-30 Data Recovery Program Data recovery program enables to re-program the program data itself which is transferred from external to different page address in same bank. Program to newly specified page address is executed by writing 10h command following 85h command and address for re-programming with 4 cycles as well as copy back program ...

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... HN29V1G91T-30 To program, update the data next, then erase, and then re-programming. R/* I/O 80h CA × × 2 Data Program1 1 R/* t BERS I/O 60h RA × 2 D0h Erase 3 Specify a page in the same bank same setting 1. 1 Page M Program1 80h−CA1−RA1−Data−10h 85h−CA2−RA2−Data−85h−CA3−Data RA1 = PageM To program, erase next, then update the data, and then re-programming ...

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... HN29V1G91T-30 Program Data Input in Erase Busy Program Data input in Erase Busy enables to program the data of any page address during busy status in erase operation possible to program the data in both block erase mode and multi bank block erase mode if they are in busy state. ...

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... HN29V1G91T-30 Program data input in multi bank program mode (In case of completing data input during busy status) Note: 1. Status command available Program data input in multi bank program mode (In case of not completing data input during busy status) Note: 1. Status command available The correspondence when the erase error occurred in Program Data Input in Erase Busy mode. ...

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... HN29V1G91T-30 Program Data Input in Erase Busy (recommend pattern when error occurred) Multi Bank Mode R/* 60h RA × 2 60h RA × 2 D0h I/O Block0 (Bank0), 1 Erase Block1 (Bank1) R/* t BERS I/O RA × 2 60h D0h FFh Reset 3 4 Block2 in Bank0 erase execute address infornation 1 Bank0 Bank1 Block1 ...

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... HN29V1G91T-30 Block Erase Erase operation for one block which is consisted of 2 page can be executed. One block is consisted of pageN and page(N+4) (Ex: page0 and page4, page1 and page5). Input page address (A14 = lower side, when erase block address input. IL Multi Block Erase Erase operation for one block in maximum 4 bank is executed simultaneously ...

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... HN29V1G91T-30 Power on Auto Read The data of the lowest page address can be read out serially without command and address input after power is on. Power on auto read mode is activated when V tied PRE pin must be connected to V when using power on auto read and V ...

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... HN29V1G91T-30 Status Read at Read mode The content of status register can be read out writing 70h command (status read command) and by clocking 4- in read operation. The data of memory array cannot be read out even by clocking 4- since status read mode is set after the device becomes ready. 7Fh command needs to be written in case of releasing status read mode in read operation ...

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... HN29V1G91T-30 Status Register check flow (single bank operation) NO Fail Not 1 bit error Fail 70h command status in single bank operation status Program/Erase Cache Program I/O 8 Write protect Write protect I/O 7 Ready/*KIO Ready/Busy I/O 6 Ready/*KIO True Ready/*KIO* I/O 5 Not Used Not Used I/O 4 Not Used ...

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... HN29V1G91T-30 72h command status in single bank operation status I/O 8 Write protect I/O 7 Ready/*KIO I/O 6 Program/Erase ECC check I/O 5 Erase check I/O 4 Program check I/O 3 Not Used I/O 2 Not Used I/O 1 Pass/Fail Status Register check flow (Multi bank program/erase) read errorstatus register *1 NO Fail Not 1 bit error Fail NO Error bank check end Rev ...

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... HN29V1G91T-30 71h Command Status in Multi Bank Operation status I/O 8 Write protect I/O 7 Ready/*KIO I/O 6 Ready/*KIO I/O 5 Bank3 Pass/Fail I/O 4 Bank2 Pass/Fail I/O 3 Bank1 Pass/Fail I/O 2 Bank0 Pass/Fail I/O 1 All Pass/Fail 73h, 74h, 75h, 76h Command Status in Multi Bank Operation / Cache program / 2page cache program status I/O 8 Write protect ...

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... HN29V1G91T-30 Status Register check flow (Cache program operation) YES Cache program I/O1=0 & I/O2=0 pass ECC impossible Cache program error so substitute operation Rev.4.00, Jun.20.2004, page 10h (Last program 70h Write read status register NO I/O6=1 Next cache program YES 71h Write read status register ...

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... HN29V1G91T-30 Status Register (Cache program operation) The status is output by writing 70h command in cache program / 2 page cache program operation. I/O1, 2 which shows pass/fail and I/O6, 7 which shows Ready/*KIO is output OR data of 2 page address which programs simultaneously. In other words, if either 2 page address is Busy status, I/O6 or I/O7 outputs “ ...

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... HN29V1G91T-30 73h, 74h, 75h, 76h command status in Cache program / 2page cache program operation status I/O 8 Write protect I/O 7 Ready/*KIO I/O 6 Program/Erase ECC check (N or N-1) I/O 5 Erase check (N or N-1) I/O 4 Program check (N or N-1) I/O 3 Not Used I/O 2 Pass/Fail (N-1) I/O 1 Pass/Fail (N) Rev.4.00, Jun.20.2004, page Output Protect: 0 Not Protect: 1 ...

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... HN29V1G91T-30 Reset operation This device can enter standby mode interrupting each operation mode by writing FFh command (reset command) during each operation. Page address data during program operation, block data during erase operation are not guaranteed after completing reset operation. Reset operation in the Cache program (R/* = Ready, True R/* = Busy) ...

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... HN29V1G91T-30 Reset operation in the Program I/O 80h/85h 10h/15h R/* Reset operation in the Erase I/O 60h D0h R/* Reset operation in the Read I/O 00h 30h/31h/35h R/* This device can enter deep standby mode interrupting each operation mode by making 4-5 pin low during each operation. Page address data during program operation, block data during erase operation are not guaranteed after completing reset operation ...

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... HN29V1G91T-30 Reset operation in the Erase 60h D0h I/O R/* 4-5 Note: 1. Power on sequence. Reset operation in the Read 00h 30h/31h/35h I/O R/* 4-5 Note: 1. Power on sequence. Rev.4.00, Jun.20.2004, page Erase busy Erase start t RSTE Read busy Read start t RSTR min RSTE * 1 t min RSTR ...

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... HN29V1G91T-30 Usage for the low level prohibits the erase operation and the program operation. When use 92, use it as follows. Program operation 9- I/O 92 R/* t WWS Prohibition of the Program operation 9- I/O 92 R/* t WWS Rev.4.00, Jun.20.2004, page 80h/85h 10h/15h 80h/85h 10h/15h ...

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... HN29V1G91T-30 Erase operation 9- I/O 92 R/* t WWS Prohibition of the Erase operation 9- I/O 92 R/* t WWS Rev.4.00, Jun.20.2004, page 60h D0h/D2h/D3h 60h D0h/D2h/D3h t WWH t WWH ...

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... HN29V1G91T-30 Status Transition PRE=L Power On & Power On Power On Read Power On Read 2nd Access State FFH or 2Kbyte Read ID Read Operation End 00H 30H, 31H Copy Back Program Operation1 (Read) Standby +- (4-5=H, +-=H) Output disable (+-=L) 06H 05H Random Output Operation E0H 2nd Access State End ...

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... HN29V1G91T-30 Erase Address Setup Erase Verify Address Setup 60H Input Setup FFH Erase Operation D0H FFH Operation End Erase Verify Operation D2H D3H FFH Operation End Program Address Setup +- 80H Standby Output (4-5=H, disable +-=H) (+-=L) Random Data Input Setup 85H Copy Back Program Operation2 (Program) ...

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... HN29V1G91T-30 Absolute Maximum Ratings Parameter V voltage CC V voltage SS All input and output voltage Operating temperature range Storage temperature range Notes: 1. Relative −2.0 V for pulse width with 20ns or less. in out 3. Device Storage temperature before programming. Capacitance Parameter Symbol Input capacitance ...

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... HN29V1G91T-30 DC Characteristics ( +70°C) CC Parameter Symbol Min Operating V voltage Operating V current I CC CC1 (Read) I CC2 Operating V current I CC CC3 (Program) I CC4 Operating V current I CC CC5 (Erase) I CC6 Standby current (TTL) I SB1 Standby current (CMOS) I SB2 Deep Standby current (CMOS) ...

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... HN29V1G91T-30 AC Characteristics ( +70°C) CC Test Conditions • Input pulse levels: 0.4 to 2.4 V • Input rise and fall time • Input and output timing levels: 1 1.5 V • Output load: 1TTL GATE and 50 pF (3.0 V ± 10%) 1TTL GATE and 100 pF (3.3 V ± 10%) ...

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... HN29V1G91T-30 AC Timing Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to 4- Delay (ID Read) ALE to 4- Delay (Read cycle) CLE to 4- Delay (Read cycle) Ready to 4- Low 4- Pulse Width 9- High to Busy Read cycle time 4- Access Time +- Access Time 4- High to Output Hi-Z ...

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... HN29V1G91T-30 Timing Waveform Command Latch Cycle Address Latch Cycle Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Input Data Latch Cycle Serial Access Cycle after Read (CLE = ALE = L) 1. The time until it becomes Hi-Z depends on the earliest signal which +- and high. Note: Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Invalid input cycle +- ALE CLE 9- I/O1 to I/O8 Invalid output cycle +- ALE CLE 4- I/O1 to I/O8 Rev.4.00, Jun.20.2004, page CHWS WHCH D IN (Invalid RHCH CHRS ...

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... HN29V1G91T-30 Status Read Cycle Note: 1. 70h: Single Bank operation Status 72h: Single Bank operation Error Status 71h: Multi Bank operation Status 73h: Multi Bank operation / Bank0 Error Status 74h: Multi Bank operation / Bank1 Error Status 75h: Multi Bank operation / Bank2 Error Status 76h: Multi Bank operation / Bank3 Error Status Rev ...

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... HN29V1G91T-30 Read Operation Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Read Operation (Intercepted by +-) CLE +- ALE 4- I/Ox 00h CA1 CA2 Column address N R/* Rev.4.00, Jun.20.2004, page CLR AR2 RA1 RA2 30h D OUT Row address Busy t CHZ N+1 D N+2 OUT OUT ...

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... HN29V1G91T-30 Random Data Output in a Page Note: 1. The head column address can be specified over and over. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Read Notes maximum 4 bank from Bank0 to Bank3 can be repeated. 2. Read out specified bank repeated over and over within the same page setup. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Page program Operation Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Page Program Operation with Random Data Input Note repeated over and over within the same page setup. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Program (1/2) Note maximum 4 bank from Bank0 to Bank3 can be repeated. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Program (2/2) Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Program Operation with Random Data Input (1/2) Note: 1. Maximum three times repeatable. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Program Operation with Random Data Input (2/2) Note: 1. Maximum three times repeatable. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Cache Program Notes: 1. There is no limitation in the number of Page address which can specify consecutively. 2. Don’t specify a Page address inside the same bank consecutively. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 2 Page Cache Program (1/2) Note: 1. Don’t specify a Page address inside the same bank consecutively. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 2 Page Cache Program (2/2) Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Copy Back Program Operation Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Copy Back Program with Data Output (1/2) Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Copy Back Program with Data Output (2/2) Note: 1. Updating copy data Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Copy Back Program (1/3) Notes: 1. Specifying the address of a source of copy. 2. Specifying the address of a source of copy maximum 4 bank can be specified. 4. Read out the data of a source of copy. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Copy Back Program (2/3) Note: 1. Updating a source data which did Copy Back Read. Specifying Page address for post-copy. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Copy Back Program (3/3) Note: 1. Updating a source data which did Copy Back Read. Specifying Page address for post-copy. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Program Data Input in Erase busy Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Block Erase Operation Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Block Erase Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Page mode Erase Verify Block mode Erase Verify Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Page mode Erase verify Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Multi Bank Block mode Erase verify Note: 1. Possible to specify maximum 4 Bank from Bank 0 to Bank3. Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Read ID Operation Rev.4.00, Jun.20.2004, page ...

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... HN29V1G91T-30 Power on Auto Read CLE ALE 9- 92 PRE 4-5 R/* 4- I/O Rev.4.00, Jun.20.2004, page CEA t VRS t VRS VRDY BSY PON REA ...

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... HN29V1G91T-30 Power on and off sequence 2 don t care +-, 9 VRS 92 CLE, ALE PRE t VRS 4-5 t VRDY invalid R/* Rev.4.00, Jun.20.2004, page BSY operation t PON 2.7 V don t care don t care ...

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... HN29V1G91T-30 Deep Standby Mode Standby state +- t CSD 4-5 R/* Operation state +- 4-5 t RST R/* Rev.4.00, Jun.20.2004, page Deep standby state Power on state 100 ns min t BSY Deep standby state Power on state t VRS t min RST t BSY Standby state t PON Standby state t PON ...

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... HN29V1G91T-30 Notes on usage 1. Prohibition of undefined command input The commands listed in the command definition can only be used in this device prohibited to issue a command that is not defined in the list undefined command is issued, the data held in the device may be lost. Only the commands defined can be issued, in only defined timings. Otherwise, illegal operations may occur ...

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... HN29V1G91T-30 erase/program/read operation, the command operation is forced to terminate and the applied page data is not guaranteed. 8. Notes on the power supply down Please do not turn off a power supply in erase busy operation required to take the following measures on system side for expected power down. ...

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... HN29V1G91T-30 9. Unusable Block Initially, the HN29V1G91T includes unusable blocks. The usable blocks must be distinguished from the usable blocks bye the system as follows. 1. Confirm the blocks which cannot be used after mounting on the system. The following data is written on each page of the blocks which can be used. One block is composed of two pages, and following data is written in both pages commonly (Refer to “ ...

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... HN29V1G91T-30 10. Measures for don’t care in timing waveforms for Program Data Input in Erase Busy The timing waveforms in any mode is specified “Don’t care”, during +- = H other control signals become “Don’t care”. When +- = H, specify ALE and CLE = H, 9- and ...

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... HN29V1G91T-30 Package Dimensions HN29V1G91T-30 (TFP-48DA) 12.00 12.40 Max 0.50 *0.22 ± 0.08 0.08 M 0.20 ± 0.06 0.45 Max 0.10 *Dimension including the plating thickness Base material dimension Rev.4.00, Jun.20.2004, page January, 2003 0.80 20.00 ± 0.20 0 ˚ – 8 ˚ 0.50 ± 0.10 Package Code TFP-48DA JEDEC Conforms JEITA Conforms Mass (reference value) ...

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... VRS Change of the figure of Read Operation (Intercepted by +-) 57 63 Change of the figure of Multi Bank Program (2/2) 84 Change of the figure of Deep Standby Mode Notes on usage: Change of 1 HN29V1G91T-30 Data Sheet (R/*) Min CHWS WHCH , WWS WWH , Change of Test conditions ...

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Rev. Date Contents of Modification Page Description 1.00 Dec. 08, 2003 Deletion of Preliminary  2 Change of the description of Wear leveling 48 Tstg: 0°C/+70°C to −25°C/+125°C 86 Notes on usage: Change of 8. 2.00 Dec. 19, 2003  ...

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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...