RF31 Hope Microelectronics co., Ltd, RF31 Datasheet - Page 14

• Manufacturer Part Number: RF31
• Description: Rf31 Ism Receiver
• Manufacturer: Hope Microelectronics co., Ltd

3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The RF31 communicates with the host MCU over a 3 wire SPI interface: SCLK, SDI, and nSEL. The host
MCU can also read data from internal registers on the SDO output pin. A SPI transaction is a 16-bit sequence
which consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field
(DATA), as demonstrated in Figure 1. The 7-bit address field supports reading from or writing to one of the 128, 8-bit
control registers. The R/W select bit determines whether the SPI transaction is a write or read transaction. If R/W = 1,
it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are
latched into the RF31 every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9. The
SCLK rate is flexible with a maximum rate of 10 MHz.
To read back data from the RF31, the R/W bit must be set to 0 followed by the 7-bit address of the register from
which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R/W = 0. The next eight negative
edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the
selected register will be available on the SDO output pin. The READ function is shown in Figure 3. After the READ
function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit
clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
Symbol
t
t
t
t
t
t
t
t
t
CH
DS
DH
DD
EN
DE
SH
t
SS
SW
CL
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Output data delay time
Output disable time
Output enable time
Select high period
Select setup time
Select hold time
Data setup time
Clock high time
Clock low time
Data hold time
Parameter
Table 9. Serial Interface Timing Parameters
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40
40
20
20
20
20
50
20
50
80
Min
Figure 2. SPI Timing
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Diagram
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R F 3 1
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