HMP8115 Intersil Corporation, HMP8115 Datasheet - Page 10

• Manufacturer Part Number: HMP8115
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

NOTE:
NOTE:
BLANK AND DVALID TIMING
DVALID is asserted when P15-P0 contain valid data. The
timing and behavior of DVALID is dependent on the output
video format and the programmed values for bit 4
(DVLD_DCYC) and bit 5 (DVLD_LTC) of the GENLOCK
CONTROL register 04
format sections that follow for the specific behavior for
DVALID.
BLANK is used to determine if the HMP8115 is generating
active video data. BLANK should be used in conjunction with
DVALID to capture digital data from the decoder. BLANK,
DVALID and the video data are output after the internal pipe-
line latency and synchronous with the rising edge of CLK2.
RECTANGULAR PIXELS
PAL (B, D, G, H, I,N, N
SQUARE PIXELS
PAL (B, D, G, H, I,N, N
5. The trailing edge of VSYNC is 5 1 clocks after the trailing edge of HSYNC is to be VMI compatible and to indicate a transition to an odd field.
6. The trailing edge of VSYNC is 5 1 clocks after the leading edge of HSYNC to be VMI compatible and to indicate a transition to an even field.
VIDEO STANDARD
NTSC (M), PAL (M)
NTSC (M), PAL (M)
HSYNC
VSYNC
VIDEO
INPUT
LINE #
FIELD
HSYNC
VSYNC
LINE #
VIDEO
INPUT
FIELD
FIGURE 7. PAL(B,D,G,H,I,N,N
FIGURE 8. PAL(B,D,G,H,I,N,N
(MSB/LSB)
621
309
C
C
)
)
H
. Refer to the specific output video
PIXELS/
ACTIVE
622
310
LINE
720
720
640
768
TABLE 2. TYPICAL VALUES FOR HBLANK AND VBLANK REGISTERS
‘EVEN’ FIELD
‘ODD’ FIELD
C
311
C
PIXELS/
TOTAL
623
) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION
) HSYNC, VSYNC AND FIELD TIMING DURING AN ODD TO EVEN FIELD TRANSITION
LINE
858
864
780
944
312
624
863 (035F
779 (030B
943 (03AF
857 (0359
COUNT
PIXEL
LAST
313
625
HMP8115
H
H
H
H
)
)
)
)
10
314
842 (034A
758 (02F6
922 (039A
852 (0354
1
H_BLANK
During active scan lines BLANK is negated when the hori-
zontal pixel count matches the value in the END H_BLANK
register 32
the leading edge of the sync tip after leaving the part. BLANK
is asserted when the horizontal pixel count matches the value
in the START H_BLANK register 31
tally, BLANK is programmable with two pixel resolution.
START V_BLANK register 34
ister 35
field. During inactive scan lines, BLANK is asserted during
the entire scan line. Half-line blanking of the output video
cannot be done. Reference Figure 9 for active video timing
and use Table 2 for typical blanking programming values.
(31H/30H)
START
‘ODD’ FIELD
‘EVEN’ FIELD
315
H
H
H
H
H
2
)
)
)
)
determine which scan lines are blanked for each
H
. A count of 00
H_BLANK
122 (7A
132 (84
118 (76
154 (9A
316
3
(32H)
END
H
H
H
H
)
)
)
)
317
H
4
corresponds to the 50% point of
H
/33
259 (0103
310 (0136
259 (0103
310 (0136
V_BLANK
(34H/33H)
START
H
318
H
and END V_BLANK reg-
5
/30
H
H
H
H
H
. Note that horizon-
)
)
)
)
319
6
V_BLANK
19 (13
22 (16
19 (13
22 (16
(35H)
END
320
7
H
H
H
H
)
)
)
)