HMP8115 Intersil Corporation, HMP8115 Datasheet - Page 11

• Manufacturer Part Number: HMP8115
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

NOTE:
PIXEL OUTPUT PORT
Pixel data is output via the P0-P15 pins. Refer to Table 3 for
the output pin definition as a function of the output mode.
8-BIT YCbCr OUTPUT
The DVALID output pin may be configured to operate in one
of two ways. The configuration is determined by the
DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register
04
If DVLD_LTC=0, the DVALID output is continuously asserted
during the entire active video time on active scan lines if CLK2
is exactly 2x the desired output sample rate. DVALID being
asserted indicates valid pixel data is present on the P15-P8
pixel outputs. DVALID is never asserted during the blanking
intervals. Refer to Figure 10.
7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards.
H
PIN NAME
.
P10
P11
P12
P13
P14
P15
LINES/FRAME
(NTSC, PAL M)
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
480 ACTIVE
8-BIT, 4:2:2, YCbCr
LINES 1 - 22 NOT ACTIVE
LINES 263 - 284 NOT ACTIVE
Y0, Cb0, Cr0
Y1, Cb1, Cr1
Y2, Cb2, Cr2
Y3, Cb3, Cr3
Y4, Cb4, Cr4
Y5, Cb5, Cr5
Y6, Cb6, Cr6
Y7, Cb7, Cr7
240 ACTIVE LINES
240 ACTIVE LINES
0
0
0
0
0
0
0
0
(LINES 285 - 524)
(LINES 23-262)
ACTIVE PIXELS
TOTAL PIXELS
PER FIELD
PER FIELD
NTSC M
NOT ACTIVE
LINE 525
FIGURE 9. TYPICAL ACTIVE VIDEO REGIONS
16-BIT, 4:2:2, YCbCr
TABLE 3. PIXEL OUTPUT FORMATS
Cb0, Cr0
Cb1, Cr1
Cb2, Cr2
Cb3, Cr3
Cb4, Cr4
Cb5, Cr5
Cb6, Cr6
Cb7, Cr7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
858
720
NTSC
FRONT
PORCH
RECTANGULAR (SQUARE)
(780)
(640)
VERTICAL
BLANKING
HMP8115
NUMBER OF PIXELS
ODD FIELD
EVEN FIELD
11
If DLVD_LTC=1, DVALID has the same internal timing as the
first mode, but is ANDed with the CLK2 signal, and the result
is output onto the DVALID pin. This results in a gated CLK2
signal being output during the active video time on active
scan lines. Refer to Figure 11.
If 8-bit YCbCr data is generated, it is output following each
rising edge of CLK2. The YCbCr data is multiplexed as [Cb Y
Cr Y Cb Y Cr Y ...], with the first active data each scan line
containing Cb data. The pixel output timing is shown in Fig-
ures 10 and 11.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr.
15-BIT, RGB, (5,5,5)
SYNC AND
864
720
PORCH
BACK
PAL
G0
G1
G2
G3
G4
B0
B1
B2
B3
B4
R0
R1
R2
R3
R4
0
(944)
(768)
LINES 1 - 22 NOT ACTIVE
LINES 311 - 335 NOT ACTIVE
PAL B, D, G, H, I, N, N
288 ACTIVE LINES
288 ACTIVE LINES
(LINES 336 - 623)
16-BIT, RGB, (5,6,5)
(LINES 23 - 310)
ACTIVE PIXELS
TOTAL PIXELS
PER FIELD
PER FIELD
LINES 624-625
NOT ACTIVE
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
R0
R1
R2
R3
R4
C
LINES/FRAME
Ancillary Data,
576 ACTIVE
SAV and EAV
YCbCr Data,
Sequences
(PAL)
BT.656
0
0
0
0
0
0
0
0