HMP8116 Intersil Corporation, HMP8116 Datasheet
HMP8116
Related parts for HMP8116
HMP8116 Summary of contents
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... I Ordering Information PART NUMBER HMP8116CN HMPVIDEVAL/ISA NOTES: 1. PQFP is also known as QFP and MQFP. 2. Evaluation Board and Reference Design descriptions are in the Applications section. 1 HMP8116 NTSC/PAL Video Decoder ) video standards interface. TEMP. o RANGE ( C) PACKAGE PKG ...
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... TELETEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REAL TIME CONTROL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Host Interface HMP8116 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PCB LAYOUT CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Functional Block Diagram HMP8116 3 ...
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Functional Block Diagram (Continued) CLK (24.54, 27.0 or 29.5MHz) 4FSC CLOCK CHROMA PLL NCO CLK TO 4FSC RATIO CR[7:0] C,CVBS C,CVBS C DATA DATA LINE M DELAY U COMB X FILTER INPUT SAMPLE RATE CONVERTER Y DATA Y DATA Y,CVBS ...
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... PLL is used to maintain vertical spatial alignment. The PLLs are designed to maintain lock even in the event of VCR headswitches and multipath noise. The HMP8116 contains two 8-bit A/D converters and an I interface for programming internal registers External Video Processing Before a video signal can be digitized the decoder has some external processing considerations that need to be addressed ...
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... A composite video signal has the luma (Y) and chroma (C) information mixed in the same video signal. The Y/C separa- tion process is responsible for separating the composite video signal into these two components. The HMP8116 uti- lizes a comb filter to minimize the artifacts that are associ- ated with the Y/C separation process. ...
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... Digital Processing of Video Once the luma and chroma have been separated the HMP8116 then performs programmable modifications (i.e. contrast, coring, color space conversions, color AGC, etc.) to the decoded video signal CbCr CONVERSION The baseband U and V signals are scaled and offset to gen- erate a nominal range of 16-240 for both the Cb and Cr data ...
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... The 15-bit data may be converted to 15-bit linear RGB, using the following equations. Although the PAL speci- fications specify a gamma of 2.8, a gamma of 2.2 is normally used. The HMP8116 allows the selection of the gamma to be either 2.2 or 2.8, independent of the video standard. for gamma = 2.2: for < 0.0812* (31)((R /31)/4 ...
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... The trailing edge of VSYNC clocks after the trailing edge of HSYNC VMI compatible and to indicate a transition to an odd field. FIGURE 6. PAL(B,D,G,H,I,N,N ) HSYNC, VSYNC AND FIELD TIMING DURING AN EVEN TO ODD FIELD TRANSITION C HMP8116 its state at the beginning of each field. FIELD changes state 5 1 CLK2 cycles before the the leading edge of VSYNC. 2 ...
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... H format sections that follow for the specific behavior for DVALID. BLANK is used to determine if the HMP8116 is generating active video data. BLANK should be used in conjunction with DVALID to capture digital data from the decoder. BLANK, DVALID and the video data are output after the internal pipe- line latency and synchronous with the rising edge of CLK2 ...
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... DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register DVLD_LTC=0, the DVALID output is continuously asserted during the entire active video time on active scan lines if CLK2 is exactly 2x the desired output sample rate. DVALID being HMP8116 ODD FIELD SYNC AND BACK PORCH VERTICAL BLANKING ...
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... The tim- ing diagrams for this mode can be found in figures 11 and 12. If DVLD_LTC=0 and DVLD_DCYC=1, DVALID behaves the HMP8116 is asserted and VBIVALID is deasserted, the YCbCr outputs have a value of 16 for Y and 128 for Cb and Cr. Y ...
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... DVLD NOTE: 14. BLANK is asserted per Figure 8. FIGURE 12. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0) HMP8116 DVALID is asserted. Either linear or gamma-corrected RGB data may be output. The pixel output timing is shown in Fig- ures 11 to 14. BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2 ...
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... BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD are output following the rising edge of CLK2. For proper operation, CLK2 must be exactly 2x the desired output sample rate. The DVALID output is continuously asserted during the entire active video time. HMP8116 ...
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... V: “1” during vertical blanking 26. H: “0” at SAV (start of active video); “1” at EAV (end of active video) Advanced Features In addition to digitizing an analog video signal the HMP8116 has hardware to process different types of Vertical Blanking Interval (VBI) data as described in the following sections. ...
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... During WSS capture (ITU-R BT.1119 and EIAJ CPX-1204), the scan lines containing WSS information are monitored. If WSS is enabled and WSS data is present, the WSS data is HMP8116 loaded into the WSS data registers. Detection of WSS The WSS decoder monitors the appropriate scan lines look- ing for the run-in and start codes used by WSS ...
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... WSS_EVEN_A and WSS_EVEN_B registers set to “0” after the data has been read out. BT.656 ANCILLARY DATA Through the BT.656 interface the HMP8116 can generate non-active video data which contains CC, WSS, teletext or CLK VBIVALID ...
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... WSS CRC data = “00 0000” during PAL operation. 33. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. TELETEXT The HMP8116 supports ITU-R BT.653 625-line and 525-line teletext system B, C and D capture. NABTS (North American Broadcast Teletext Specification) is the same as BT.653 525- line system C, which is also used to transmit Intel Intercast™ ...
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... Note both “sliced” and “raw” VBI data may be available on the same line. During NTSC operation, the first possible line of VBI data is HMP8116 DATA PACKET Bit 0 FIGURE 17. TELETEXT VBI VIDEO SIGNAL ...
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... P8-P13. 42. CRC = Sum of P8-P14 of Data ID through last user data word. Preset to all zeros, carry is ignored. HMP8116 The PSW bit is always a “0” for NTSC encoding. During PAL encoding, it indicates the sign of V (“0” = negative; “1” = pos- itive) for that scan line ...
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... The bit descriptions of the control registers are listed in Tables 8-57. The HMP8116 supports the fast-mode (up to 400 kbps) I interface consisting of the SDA and SCL pins. The device acts as a slave for receiving and transmitting data over the serial interface ...
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... HMP8116 Control Registers TABLE 9. 8116 REGISTER SUMMARY SUB- ADDRESS CONTROL REGISTER 00 PRODUCT INPUT FORMAT H 02 OUTPUT FORMAT H 03 OUTPUT CONTROL H 04 GENLOCK CONTROL H 05 ANALOG INPUT CONTROL H 06 COLOR PROCESSING H 07 RESERVED H 08 LUMA PROCESSING H 09 Reserved H 0A SLICED VBI DATA ENABLE ...
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... HMP8116 23 ...
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... Output black field 11 = Output 75% color bars 0 Vertical Pixel This bit specifies whether or not the chrominance pixels have a half- Siting line pixel offset from their associated luminance pixels Half-line offset 1 = Aligned HMP8116 TABLE 10. PRODUCT ID REGISTER SUB ADDRESS = 00 H DESCRIPTION SUB ADDRESS = 01 H DESCRIPTION ) PAL ...
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... Active high (high during vertical sync) 1 DVALID Polarity 0 = Active low (low during valid pixel data Active high (high during valid pixel data) 0 VBIVALID 0 = Active low (low during VBI data) Polarity 1 = Active high (high during VBI data) HMP8116 SUB ADDRESS = 03 H DESCRIPTION 25 RESET STATE ...
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... This bit specifies the number of missing vertical sync pulses before the device goes into Detect Select the vertical lock acquisition mode pulses pulse 1-0 CLK2 Frequency This bit indicates the frequency of the CLK2 input clock 24.54MHz 01 = 27.0MHz 10 = 29.5MHz 11 = Reserved HMP8116 SUB ADDRESS = 04 H DESCRIPTION . H 26 RESET STATE ...
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... CbCr data (“1”). To avoid color shifts when changing contrast, this bit should be a “1” Contrast controls only Y data 1 = Contrast controls Y and CbCr data 0 Color Lowpass This bit selects the bandwidth of the CbCr data. Filter Select 0 = 850kHz 1 = 1.5MHz HMP8116 SUB ADDRESS = 05 H DESCRIPTION SUB ADDRESS = 06 H DESCRIPTION 27 RESET ...
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... WSS enabled for even fields: line 283 for NTSC, line 280 for (M) PAL, or line 336 for ( WSS enabled for both odd and even fields 3-2 Sliced 00 = Teletext disabled Teletext 01 = Teletext system B enabled Enable 10 = Teletext system C enabled 11 = Teletext system D enabled 1-0 Reserved HMP8116 SUB ADDRESS = 08 H DESCRIPTION SUB ADDRESS = 0A H DESCRIPTION ) PAL C ) PAL C ) PAL C ...
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... WSS detected 3 VBI Teletext This bit is read-only. Data written to this bit is ignored. Detect Status 0 = Teletext not detected during vertical blanking interval 1 = Teletext detected during vertical blanking interval 2-0 Reserved HMP8116 SUB ADDRESS = 0B H DESCRIPTION TABLE 20. VBI DATA STATUS REGISTER SUB ADDRESS = 0C H DESCRIPTION 29 ...
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... Auto Detect This bit is set when automatic detection of the video standard is enabled, and the Video Standard HMP8116 has determined the input format of the video signal. This bit is read-only. Data Status written to this bit is ignored Video standard not determined on selected video input 1 = Video standard determined on selected video input TABLE 22 ...
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... NO. FUNCTION 7-0 Raw VBI Start Specifies where to start generating raw VBI data in two sample clock steps from the 50% Count point of the leading edge of HSYNC. HMP8116 SUB ADDRESS = 10 H DESCRIPTION SUB ADDRESS = 11 H DESCRIPTION , CNT1, CNT2 and 00H. Where CNT1 = even parity bar, even parity[5-0], ...
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... Bit 2 corresponds to line 27 (odd field) and 290 (even field) for 525 line systems and to line 23 (odd field) and 336 (even field) for 625 line systems. HMP8116 SUB ADDRESS = 13 H DESCRIPTION ...
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... A value of 1x (“0110 0111”) has no effect. Refer to the look-up table following register definitions for other values to load for different gains. This register is ignored unless the video gain control mode selection is “fixed gain control”. HMP8116 TABLE 31. BRIGHTNESS REGISTER SUB ADDRESS = 18 H DESCRIPTION TABLE 32 ...
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... FUNCTION 15-8 Odd Field If odd field captioning is enabled and present, this register is loaded with the second eight Caption Data bits of caption data on line 18, 21, or 22. Data written to this register is ignored. HMP8116 TABLE 37. SHARPNESS REGISTER SUB ADDRESS = 1E H DESCRIPTION TABLE 38. HOST CONTROL REGISTER ...
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... If even field WSS is enabled and present, this register is loaded with the first eight bits of WSS Data WSS information on line 280, 283, or 336. Bit 0 corresponds to the first bit of WSS infor- mation. Data written to this register is ignored. HMP8116 TABLE 42. SUB ADDRESS = 22 H DESCRIPTION ...
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... It specifies the line number to assert BLANK each field. For NTSC operation, it occurs on line ( odd fields and line (n + 268) on even fields. For PAL operation, it occurs on line ( odd fields and line (n + 318) on even fields. HMP8116 SUB ADDRESS = 28 H DESCRIPTION ...
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... H H 0.64 161/A1 0.81 127/ 0.65 159/9F 0.82 206/ 0.66 156/9C 0.83 206/ HMP8116 SUB ADDRESS = 34 H DESCRIPTION TABLE 55. END V_BLANK REGISTER SUB ADDRESS = 35 H DESCRIPTION TABLE 56. END HSYNC REGISTER SUB ADDRESS = 36 H DESCRIPTION . H SUB ADDRESS = 37 H DESCRIPTION Video Reg. Video Reg. Video ...
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... Digital Ground Plane All GND pins on the HMP8116 should be connected to the digital ground plane of the board. Analog Ground Plane A separate analog ground plane for the HMP8116 is recom- mended ...
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... EVALUATION BOARD HMPVIDEVAL/ISA The HMPVIDEVAL/ISA evaluation board allows connecting the HMP8116 into a PC ISA slot for evaluation. It includes the HMP8115 NTSC/PAL decoder, 3MB of VRAM, and a NTSC/PAL encoder. The board accepts composite or S- video input and displays video on a standard TV. The ISA ...
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... Input Logic High Voltage Input Logic Low Voltage Output Logic High Voltage HMP8116 Thermal Information Thermal Resistance (Typical, See Note 1) PQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 0.5V Maximum Power Dissipation CC HMP8116CN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9W Maximum Storage Temperature Range . . . . . . . . . .-65 Maximum Junction Temperatures . . . . . . . . . . . . . . . . . . . . . 150 Maximum Lead Temperature (Soldering 10s 300 5.0V, T ...
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... Amplitude (Burst Amplitude) Video Input Impedance Video Input Bandwidth ADC Input Range ADC Integral Nonlinearity ADC Differential Nonlinearity VIDEO PERFORMANCE Differential Gain Differential Phase Hue Accuracy Color Saturation Accuracy HMP8116 o = 5.0V (Continued SYMBOL TEST CONDITION 3mA Min OL ...
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... This should not be confused with Clock Jitter, since the HMP8116 does not generate the sample clock. Thus, clock jitter is solely depen- dent on the source of the CLK2 signal. The Vertical Sample Alignment parameter specifies how accurately samples align vertically from one scan line to the next. ...
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... For general information regarding Harris Semiconductor and its products, call 1-800-4-HARRIS NORTH AMERICA Harris Semiconductor P. O. Box 883, Mail Stop 53-210 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 HMP8116 Q80.14x20 80 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE SYM- BOL ...