HMP41GF7MMP8C Hynix Semiconductor, HMP41GF7MMP8C Datasheet - Page 11

• Manufacturer Part Number: HMP41GF7MMP8C
• Description: 240pin Fully Buffered Ddr2 Sdram Dimms
• Manufacturer: Hynix Semiconductor

Rev 0.1 / May 2008
Basic Functionality
1. Advanced Memory Buffer Overview
The Advanced Memory Buffer refernce design complies with the JEDEC FB-DIMM Archtecture and Protocol
Specification.
2. Advanced Memory Buffer Functionality
2.1 Advanced Memory Buffer
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2.2 Transparent Mode for DRAM Test Support
In this mode, the Advanced Memory Buffer will provide lower speed tester access to DRAM pins through
the FB-DIMM I/O pins. This allows the tester to send and arbitrary test pattern to the DRAMs. Transparent
mode only supports a maximum DRAM frequency equivalent to DDR2 400.
Transparent mode functionality:
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2.3 DDR2 SDRAM
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Supports channel initialization procedures ans defined in the initialization chapter of the FB-DIMM
Architecture and Protocol Specification to align the clocks and ther frame boundaries verify channel
connectivity and identify AMB DIMM position.
Supports ther forwarding of southbound and northbound frames, servicing requests dircted to DIMM,
as defined in the protocol chapter, and merging the return data into the northbound frames.
If ther AMB resides on the last DIMM in the channel, the AMB initializes northbound frames.
Detects errors on the channel and reports them to ther host memory controller.
Acts as DRAM memory buffer for all read, write and configuration acsesses addressed to the DIMM.
Provides a read buffer FIFO and a write buffer FIFO.
Supports an SMBus protocol interface for access to the AMB configuration registers.
Provides logic to support MEMBIST and IBIST Design for Test functions.
Provides a register interface for ther thermal sensor and status indicator.
Functions as a repeater to extend the maximum length of FBD Links.
Reconfigures FB-DIMM inputs from differential high speed link recievers to two single ended lower
speed receivers(~200 Mhz)
These inputs directly control DDR2 Command/Adress and input data that is replicated to all DRAMs
Used low speed direct drive FB-DIMM outputs to bypass high speed Parallel/Serial circuitry and
provide test results back to tester
Supports DDR2 at speeds of 533,667 and 800 MT/s
Supports 512Mb devices in x4 and x8 configurations
72 bit DDR2 SDRAM memory array
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240pin Fully Buffered DDR2 SDRAM DIMMs
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