HMP41GF7MMP8C Hynix Semiconductor, HMP41GF7MMP8C Datasheet - Page 3

• Manufacturer Part Number: HMP41GF7MMP8C
• Description: 240pin Fully Buffered Ddr2 Sdram Dimms
• Manufacturer: Hynix Semiconductor

Rev 0.1 / May 2008
Input/Output Functional Description
DNU/M_Test
Pin Name
PN[13:0]
PN[13:0]
SN[13:0]
SN[13:0]
VID[1:0]
VDDSPD
PS[9:0]
PS[9:0]
SS[9:0]
SS[9:0]
SA[2:0]
RESET
VDD
SCK
SCK
SDA
RFU
VCC
SCL
VTT
VSS
Input / Output
- / Analog
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
type
-
Active Low
Polarity
Negative
Negative
Negative
Negative
Negative
Positive
Positive
Positive
Positive
Positive
- / 0.9V
+1.5V
+1.8V
+0.9V
+3.3V
-
-
-
-
-
System clock input
System clock input
Primary Northbound Data
Primary Northbound Data
Primary Southbound Data
Primary Southbound Data
Secondary Northbound Data
Secondary Northbound Data
Secondary Southbound Data
Serial Presence Datect (SPD) Clock Input
SPD Data Input / Output
SPD Address inputs, also used to select the DIMM number in the AMB
Voltage ID: These pins must be unconnected for DDR2-based Fully buff-
ered DIMMs
AMB reset signal
Reserved for Future Use
AMB Core Power and AMB channel Interface Power(1.5volt)
DRAM Power and AMB DRAM I/O Power
DRAM Address/Command/Clock Termination Power(VDD/2)
SPD Power
Ground
The DNU/M_Test pin provides an external connection on R/Cs A-D for
testing the margin of Vref which is produced by a voltage divider on the
module. It is not intended to be used in normal system operation and
must not be connected(DNU) in a system. This test pin may have other
features on future card designs and if it does, will be included in this
specification at that time.
Secondary Southbound Data
1
240pin Fully Buffered DDR2 SDRAM DIMMs
Function Description
Total
Count
240
14
14
10
10
10
16
80
10
14
14
24
1
1
1
1
3
2
1
8
4
1
1
3