HMP41GF7MMP8C Hynix Semiconductor, HMP41GF7MMP8C Datasheet - Page 13

• Manufacturer Part Number: HMP41GF7MMP8C
• Description: 240pin Fully Buffered Ddr2 Sdram Dimms
• Manufacturer: Hynix Semiconductor

Rev 0.1 / May 2008
4. Interfaces
Below Figure illustrates the AMB and all of its interfaces.They consits of two FB-DIMM links, one DDR2
channel and an SMBus interface. Each FB-DIMM link connects the AMB to a host meory controller or an
adjacent FB-DIMM. Ther DDR2 channel supports direct connection to the DDR2 SDRAMs on a Fully
Buffered DIMM.
4.1 FBD High-Speed Differential Point-to-Point Link (at 1.5V) Interfaces
The Advanced Memory Buffer supports one FBD channel consisting of two bidirectional link interfaces
using high speed differential point-to-point electrical signaling.
The southbound input link is 10 lanes wid and carries commands and write data from the host memory
controller or the adjacent DIMM in the host direction. The southbound output link forwards this same data
to the next FBD.
The northbound input link is 13 to 14 lanes wide and carries read return data or status information from
the next FB-DIMM in the chain back towards the host. The northbound output link forwards this informa-
tion back towards the host and multiplexes in any read return data or status information that is generated
internally.
4.2 DDR2 Channel
The DDR2 channel on the Advanced Memory Buffer supports direct connection to DDR2 SDRAMs. The
DDR2 channel supports two ranks of eight banks with 16 row/column request, 64 data signals, and eight
check-bit signals.
There are two copies of address and command signals to support DIMM routing and electrical require-
ments. Four transfer bursts are driven on the data and check-bit lines at 800 MHz. Propagation delalys
between read data/check-bit strobe lanes on a given channel can differ. Each strobe can be calibrated by
hardware state machines using write/read trial and error. Hardware aligns the read data and check-bits to
a single core clock. The Advanced Memory Buffer provides four copies of the command clock phase refer-
ences(CLK[3:0]) and write data/check-bit strobes(DQSs) for each DRAM nibble.
O u t L in k
S B F B D
N B F B D
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A d v a n c e d M e m o ry B u ffe r In te rfa c e s
M e m o ry In te rfa ce
1
240pin Fully Buffered DDR2 SDRAM DIMMs
A M B
C h a n n e l
D D R 2
S M B u s
O u t L in k
S B F B D
N B F B D
In L in k
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