MCF5480 Freescale Semiconductor, Inc, MCF5480 Datasheet
MCF5480
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... Freescale Semiconductor Data Sheet MCF548x ColdFire Microprocessor Supports MCF5480, MCF5481, MCF5482, MCF5483, MCF5484, and MCF5485 Features list: • ColdFire V4e Core – Limited superscalar V4 ColdFire processor core – 200MHz peak internal core frequency (308 MIPS [Dhrystone 2.1] @ 200 MHz) – Harvard architecture – ...
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Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 Thermal ...
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ColdFire V4e Core FPU, MMU EMAC 32K D-cache 32K I-Cache Interrupt Controller Watchdog Timer Slice Timers Timers x 4 FlexCAN x 2 DSPI Freescale Semiconductor DDR SDRAM PLL Interface XL Bus Memory Arbiter Controller XL Bus Master/Slave ...
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Maximum Ratings 1 Maximum Ratings Table 1 lists maximum and minimum ratings for supply and operating voltages and storage temperature. Operating outside of these ranges may cause erratic behavior or damage to the processor. Rating External (I/O pads) supply voltage ...
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Thermal Resistance Table 3 lists thermal resistance values. Characteristic 324 pin TEPBGA — Junction to ambient, natural convection 388 pin TEPBGA — Junction to ambient, natural convection Junction to ambient (@200 ft/min) Junction to board Junction to case Junction ...
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Hardware Design Considerations Table 4. DC Electrical Specifications (continued) Characteristic USB PLL operation voltage range Input high voltage SSTL 3.3V/2.5V 2 Input low voltage SSTL 3.3V/2.5V Input high voltage 3.3V I/O pins Input low voltage 3.3V I/O pins Output high ...
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NOTES: 1. IVDD should not exceed EVDD or SD VDD by more than 0.4V at any time, including power-up. 2. Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to 0.9V, then separate for completion ...
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Hardware Design Considerations 4.3 General USB Layout Guidelines 4.3.1 USB D+ and D- High-Speed Traces 1. High speed clock and the USBD+ and USBD- differential pair should be routed first. 2. Route USBD+ and USBD- signals on the top layer ...
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USB Power Filtering To minimize noise, an external filter is required for each of the USB power pins. The filter shown in connected between the board • The resistor and capacitors should be placed as ...
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Output Driver Capability and Loading 4.4.1 Bias Resistor The USBRBIAS resistor should be placed as close to the dedicated USB 2.0 pins as possible. The tolerance should be ±1%. 5 Output Driver Capability and Loading Table 6 lists values for ...
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PLL Timing Specifications The specifications in Table 7 are for the CLKIN pin. Num C1 Cycle time C2 Rise time (20% of Vdd to 80% of vdd) C3 Fall time (80% of Vdd to 20% of Vdd) C4 Duty ...
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Reset Timing Specifications 7 Reset Timing Specifications Table 9 lists specifications for the reset timing parameters shown in Num RSTI and FlexBus data lines are synchronized internally. Setup and hold times must be met only ...
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FlexBus AC Timing Characteristics The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock. Num Frequency of Operation FB1 Clock Period (CLKIN) FB2 Address, Data, and Control Output Valid ...
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FlexBus CLKIN AD[X:0] AD[31:Y] R/W ALE TSIZ[1:0] FBCSn, BE/BWEn FB1 A[X:0] FB2 A[31:Y] DATA FB4 TSIZ[1:0] FB6 Figure 11. FlexBus Read Timing ® MCF548x ColdFire Microprocessor, Rev. 4 FB3 FB5 FB7 Freescale Semiconductor ...
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CLKIN AD[X:0] AD[31:Y] R/W ALE TSIZ[1:0] FBCSn, BE/BWEn SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or double data rate (DDR) SDRAM, but it does not ...
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SDRAM Bus Symbol Characteristic Frequency of Operation SD1 Clock Period ( SD2 Clock Skew ( SD3 Pulse Width High (t ) CKH SD4 Pulse Width Low (t ) CKL SD5 Address, CKE, CAS, RAS, WE, BA, ...
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SD2 SDCLK0 SD2 SDCLK1 SDCSn,SDWE, CMD RAS, CAS SD5 SDADDR, ROW SDBA[1:0] SDDM SDDATA SD2 SDCLK0 SD2 SDCLK1 SDCSn,SDWE, CMD RAS, CAS SD5 SDADDR, ROW SDBA[1:0] SDDM SDRQS (Measured at Output Pin) SDDQS (Measured at Input Pin) Delayed SDCLK SDDATA ...
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SDRAM Bus 9.2 DDR SDRAM AC Timing Characteristics When using the DDR SDRAM controller, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS ...
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Table 13. DDR Timing Specifications (continued) Symbol Characteristic DD13 DQS input read preamble width (t DD14 DQS input read postamble width (t DD15 DQS output write preamble width (t DD16 DQS output write postamble width (t 1 DDR memories typically ...
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SDRAM Bus SDCLK0 SDCLK1 SDCLK0 SDCLK1 SDCSn,SDWE, RAS, CAS DD4 SDADDR, SDBA[1:0] SDDM SDDQS SDDATA 20 DD1 DD2 DD5 CMD DD6 ROW COL WD1 WD2 WD3 WD4 Figure 16. DDR Write Timing ® MCF548x ColdFire Microprocessor, Rev. 4 DD3 DD7 ...
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SDCLK0 SDCLK1 SDCLK0 SDCLK1 SDCSn,SDWE, RAS, CAS DD4 SDADDR, SDBA[1:0] SDDQS SDDATA SDDQS SDDATA 10 PCI Bus The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please refer ...
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Fast Ethernet AC Timing Specifications Table 14. PCI Timing Specifications (continued) Num P7 PCI signals (0–50 Mhz) - Input Hold (t PCI REQ/GNT (33 < PCI ≤ 50Mhz) - Output valid (t P8 PCI REQ/GNT (0 < PCI ≤ 33Mhz) ...
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Num M1 RXD[3:0], RXDV, RXER to RXCLK setup M2 RXCLK to RXD[3:0], RXDV, RXER hold M3 RXCLK pulse width high M4 RXCLK pulse width low RXCLK (Input) RXD[3:0] (Inputs) RXDV, RXER Figure 19. MII Receive Signal Timing Diagram 11.2 MII ...
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Fast Ethernet AC Timing Specifications 11.3 MII Async Inputs Signal Timing (CRS, COL) Num M9 CRS, COL minimum pulse width CRS, COL 11.4 MII Serial Management Channel Timing (MDIO,MDC) Table 18. MII Serial Management Channel Signal Timing Num M10 MDC ...
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General Timing Specifications Table 19 lists timing specifications for the GPIO, PSC, FlexCAN, DREQ, DACK, and external interrupts. Name G1 CLKIN high to signal output valid G2 CLKIN high to signal invalid (output hold) G3 Signal input pulse width ...
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JTAG and Boundary Scan Timing 1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown interface is designed ...
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TCLK (Input) TCLK Data Inputs Data Outputs Data Outputs Data Outputs TCLK TDI, TMS, BKPT TDO TDO TDO TCLK TRST Figure 27. TRST Timing Debug AC Timing Specifications Freescale Semiconductor Figure 24. Test ...
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JTAG and Boundary Scan Timing Table 23 lists specifications for the debug AC timing parameters shown in Num D1 PSTDDATA to PSTCLK setup D2 PSTCLK to PSTDDATA hold D3 DSI-to-DSCLK setup 1 D4 DSCLK-to-DSO hold D5 DSCLK cycle time 1 ...
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DSPI Electrical Specifications Table 24 lists DSPI timings. Table 24. DSPI Modules AC Timing Specifications Name DS1 DSPI_CS[3:0] to DSPI_CLK DS2 DSPI_CLK high to DSPI_DOUT valid. DS3 DSPI_CLK high to DSPI_DOUT invalid. (Output hold) DS4 DSPI_DIN to DSPI_CLK (Input ...
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Case Drawing 17 Case Drawing 30 ® MCF548x ColdFire Microprocessor, Rev. 4 Freescale Semiconductor ...
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Freescale Semiconductor Figure 31. 388-pin BGA Case Outline ® MCF548x ColdFire Microprocessor, Rev. 4 Case Drawing 31 ...
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Revision History 18 Revision History Revision Date Number 2.2 August 29, 2005 2.3 August 30, 2005 2.4 December 14, 2005 3 February 20, 2007 4 December 4, 2007 32 Substantive Changes Table 7: Changed C1 minimum spec from 15.15 ns ...
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Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK ® MCF548x ColdFire Microprocessor, Rev ...
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