MCF5480 Freescale Semiconductor, Inc, MCF5480 Datasheet - Page 7

• Manufacturer Part Number: MCF5480
• Description: Mcf548x Coldfire Microprocessor
• Manufacturer: Freescale Semiconductor, Inc

The relationship between SD V
3.3V) and EV
4.2.1
If EV
to the EV
must power up. IV
high current in the internal ESD protection diodes. The rise times on the power supplies should be slower than 1 microsecond
to avoid turning on the internal ESD protection clamp diodes.
The recommended power up sequence is as follows:
4.2.2
If IV
There is no limit on how long after IV
not lag EV
ESD protection diodes. There are no requirements for the fall times of the power supplies.
The recommended power down sequence is as follows:
Freescale Semiconductor
1.
2.
1.
2.
DD
DD
PLL V
/SD V
Use 1 microsecond or slower rise time for all supplies.
IV
V
Drop IV
Drop EV
DD
DD
DD
DD
/SD V
, SD V
DD
going to the higher external voltages. One way to accomplish this is to use a low drop-out voltage regulator.
Power Up Sequence
Power Down Sequence
/PLL V
DD
DD
are specified relative to IV
DD
are powered down first, sense circuits in the I/O pads cause all output drivers to be in a high impedance state.
are powered up with the IV
DD
DD
DD
DD
/PLL V
/SD V
to be in a high impedance state. There is no limit to how long after EV
3.3V
2.5V
1.5V
DD
should not lead the EV
, or PLL V
NOTES:
0
and EV
Figure 3. Supply Voltage Sequencing and Separation Cautions
DD
DD
1.
2.
3.
4.
supplies
IVDD should not exceed EVDD or SD VDD by more than 0.4V
at any time, including power-up.
Recommended that IVDD/PLL VDD should track EVDD/SD VDD up to
0.9V, then separate for completion of ramps.
Input voltage must not be greater than the supply voltage (EVDD, SD VDD,
IVDD, or PLL VDD) by more than 0.5V at any time, including during power-up.
Use 1 microsecond or slower rise time for all supplies.
to 0V
DD
DD
DD
and EV
/SD V
1
going low by more than 0.4V during power down or there is undesired high current in the
DD
MCF548x ColdFire
and PLL V
DD
2
DD
DD
DD
DD
should track up to 0.9V, then separate for the completion of ramps with EV
is non-critical during power-up and power-down sequences. SD V
.
, SD V
at 0V, the sense circuits in the I/O pads cause all pad output drivers connected
DD
Supplies Stable
DD
power down before EV
, or PLL V
®
Microprocessor, Rev. 4
DD
by more than 0.4V during power ramp up or there is
DD
or SD V
EV
SD V
IV
DD
DD
DD
DD
Hardware Design Considerations
, PLL V
DD
, SD V
/SD V
must power down. IV
(2.5V)
DD
DD
DD
Time
(3.3V)
powers up before IV
DD
DD
(2.5V or
DD
should
/SD
DD
7