MTV212M64 ETC-unknow, MTV212M64 Datasheet - Page 16

• Manufacturer Part Number: MTV212M64
• Description: 8051 Embedded Monitor Controller Mtp Type
• Manufacturer: ETC-unknow

IICCTR (r/w) : IIC interface control register.
IICSTUS (r) :
INTFLG (w) :
INTFLG (r) :
Revision 1.2
* Please see the attachments about "Master IIC Receive Timing".
Reg name
SLVAADR
SLVBADR
* A write/read MBUF operation can be recognized only after 10us of the MbufI flag's rising edge.
RCABUF
RCBBUF
TXABUF
TXBBUF
IICSTUS
IICSTUS
INTFLG
INTFLG
IICCTR
INTEN
MBUF
DBUF
DDC2 = 1
MAckO = 1
S, P
WadrB = 1
WadrA = 1
SlvRWB = 1
SAckIn = 1
SLVS
SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.
MAckIn = 1
Hifreq = 1
Hbusy = 1
SlvBMI = 1
SlvAMI = 1
MbufI
00h (r/w)
05h (r/w)
Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
0Ah (w)
03h (w)
04h (w)
06h (w)
07h (w)
08h (w)
09h (w)
= 0
= 0
= , 0
= X,
= 1, X
= X, 0
IIC interface status register.
= 0
= 1
= 0
= 0
= 0
= 1
= 0
Interrupt flag.
01h (r)
02h (r)
03h (r)
06h (r)
08h (r)
addr
MYSON
TECHNOLOGY
ENSlvA
ENSlvB
MAckIn
WadrB
Will resume transfer after a read/write MBUF operation.
ACK received from the slave IIC device.
MTV212M is in DDC2 mode, write "0" can clear it.
MTV212M is in DDC1 mode.
In master receive mode, NACK is returned by MTV212M.
In master receive mode, ACK is returned by MTV212M.
Start condition when Master IIC is not during transfer.
Stop condition when Master IIC is not during transfer.
Force HSCL low and occupy the master IIC bus.
The data in RCBBUF is word address.
The data in RCABUF is word address.
Current transfer is slave transmit
Current transfer is slave receive
The external IIC host respond NACK.
The slave block has detected a START, cleared when STOP detected.
Master IIC bus error, no ACK received from the slave IIC device.
MTV212M has detected a higher than 200Hz clock on the VSYNC pin.
Host drives the HSCL pin to low.
No action.
Clear SlvBMI flag.
No action.
Clear SlvAMI flag.
No action.
Clear Master IIC bus interrupt flag (MbufI).
ETXBI
DDC2
TXBI
bit7
WadrA SlvRWB SAckIn
ERCBI ESlvBMI
Hifreq
RCBI
bit6
Master IIC receive/transmit data buffer
SlvBMI
SlvBMI
Hbusy
bit5
Slave A IIC transmit buffer
Slave B IIC transmit buffer
DDC1 transmit data buffer
- 16 -
Slave A IIC receive buffer
Slave B IIC receive buffer
ETXAI
TXAI
bit4
Slave A IIC address
Slave B IIC address
ERCAI ESlvAMI EDbufI
SLVS
RCAI
bit3
MAckO
SlvAMI
SlvAMI
bit2
MTV212M64
SlvAlsb1 SlvAlsb0
DbufI
bit1
P
(Rev. 1.2)
EMbufI
2000/07/04
MbufI
MbufI
bit0
S