MTV212M64 ETC-unknow, MTV212M64 Datasheet - Page 17

• Manufacturer Part Number: MTV212M64
• Description: 8051 Embedded Monitor Controller Mtp Type
• Manufacturer: ETC-unknow

INTEN (w) :
Mbuf (w) :
Mbuf (r) :
RCABUF (r) :
TXABUF (w) : Slave IIC block A transmit data buffer.
SLVAADR (w) : Slave IIC block A's enable and address.
RCBBUF (r) :
TXBBUF (w) : Slave IIC block B transmit data buffer.
SLVBADR (w) : Slave IIC block B's enable and address.
8. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of power supply is below 4.0V for a specific time, the LVR will generate a chip reset
signal. After the power supply is above 4.0V, LVR maintain in reset state for 144 Xtal cycle to guarantee the
chip exit reset condition with a stable X'tal oscillation.
The WatchDog Timer automatically generates a device reset when it is overflow. The interval of overflow is
0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer
function is disabled after power on reset, user can activate this function by setting WEN, and clear the timer
by set WCLR.
Revision 1.2
TXBI
RCBI
SlvBMI = 1
TXAI
RCAI
SlvAMI = 1
DbufI
MbufI = 1
ETXBI = 1
ERCBI = 1
ESlvBMI = 1
ETXAI = 1
ERCAI = 1
ESlvAMI = 1
EDbufI = 1
EMbufI = 1
ENslvA = 1
bit6-0 :
ENslvB = 1
bit6-0 :
= 1
= 1
= 1
= 1
= 1
Master IIC data shift register, after START and before STOP condition, write this register will
resume MTV212M's transmission to the IIC bus.
Master IIC data shift register, after START and before STOP condition, read this register will
resume MTV212M's receiving from the IIC bus.
Interrupt enable.
Slave IIC block A receive data buffer.
= 0
Slave IIC block B receive data buffer.
= 0
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TECHNOLOGY
Slave IIC address A to which the slave block should respond.
Slave IIC address B to which the slave block should respond.
Indicates the TXBBUF need a new data byte, clear by writing TXBBUF.
Indicates the RCBBUF has received a new data byte, clear by reading RCBBUF.
Indicates the slave IIC address B match condition.
Indicates the TXABUF need a new data byte, clear by writing TXABUF.
Indicates the RCABUF has received a new data byte, clear by reading RCABUF.
Indicates the slave IIC address A match condition.
Indicates the DDC1 data buffer need a new data byte, clear by writing DBUF.
Indicates a byte is sent/received to/from the master IIC bus.
Enable TXBBUF interrupt.
Enable RCBBUF interrupt.
Enable slave address B match interrupt.
Enable TXABUF interrupt.
Enable RCABUF interrupt.
Enable slave address A match interrupt.
Enable DDC1 data buffer interrupt.
Enable Master IIC bus interrupt.
Enable slave IIC block A.
Disable slave IIC block A.
Enable slave IIC block B.
Disable slave IIC block B.
- 17 -
MTV212M64
(Rev. 1.2)
2000/07/04