MTV212M64 ETC-unknow, MTV212M64 Datasheet - Page 20

• Manufacturer Part Number: MTV212M64
• Description: 8051 Embedded Monitor Controller Mtp Type
• Manufacturer: ETC-unknow

USBADR (r/w) :USB device address and enable.
INTFLG (w) :
INTFLG (r) :
Revision 1.2
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
USBCTR
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX0CTR
TX0CTR
TX1CTR
TX1CTR
ENUSB = 1
USBadr :
USBrstI = 1
RC0I
TX1I
TX0I
RsmI
USBrstI= 1
RC0I
TX1I
64h (r/w)
7Ch (w)
7Dh (w)
Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
= 1
= 1
7Ah (w)
7Bh (w)
7Eh (w)
7Fh (w)
65h (w)
66h (w)
70h (w)
71h (w)
72h (w)
73h (w)
74h (w)
75h (w)
76h (w)
77h (w)
78h (w)
79h (w)
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
Interrupt flag.
6Ch (r)
6Dh (r)
6Ah (r)
6Bh (r)
6Eh (r)
6Fh (r)
65h (r)
66h (r)
68h (r)
69h (r)
MYSON
TECHNOLOGY
USB device address, clear while chip reset or USB bus reset.
Indicates the USB bus reset condition.
Endpoint 0 has completed a receive transfer and save the data in RC0FIFO.
Endpoint 1 has completed a transmit transfer and empty TX1FIFO.
TX0rdy
TX0rdy
TX1rdy
TX1rdy
Enable USB function, clear while chip reset.
No action.
Clear USBrstI flag.
No action.
Clear RC0I flag.
No action.
Clear TX1I flag.
No action.
Clear TX0I flag.
No action.
Clear RsmI flag.
Susp
TX0tgl
TX0tgl
TX1tgl
TX1tgl
RsmO
EP1cfgd RC0nak
EP0stall
EP0stall
EP1stall
EP1stall
Endpoint 0 transmit FIFO 2nd byte
Endpoint 1 transmit FIFO 2nd byte
Endpoint 0 receive FIFO 2nd byte
Endpoint 0 transmit FIFO 1st byte
Endpoint 0 transmit FIFO 3rd byte
Endpoint 0 transmit FIFO 4th byte
Endpoint 0 transmit FIFO 5th byte
Endpoint 0 transmit FIFO 6th byte
Endpoint 0 transmit FIFO 7th byte
Endpoint 0 transmit FIFO 8th byte
Endpoint 1 transmit FIFO 1st byte
Endpoint 1 transmit FIFO 3rd byte
Endpoint 1 transmit FIFO 4th byte
Endpoint 1 transmit FIFO 5th byte
Endpoint 1 transmit FIFO 6th byte
Endpoint 1 transmit FIFO 7th byte
Endpoint 1 transmit FIFO 8th byte
Endpoint 0 receive FIFO 3rd byte
Endpoint 0 receive FIFO 1st byte
Endpoint 0 receive FIFO 4th byte
Endpoint 0 receive FIFO 5th byte
Endpoint 0 receive FIFO 6th byte
Endpoint 0 receive FIFO 7th byte
Endpoint 0 receive FIFO 8th byte
- 20 -
CtrRD
TX0cnt
TX1cnt
MTV212M64
(Rev. 1.2)
USBactv
2000/07/04