OM6211 NXP Semiconductors, OM6211 Datasheet - Page 29

• Manufacturer Part Number: OM6211
• Description: 48 X 84 Dot Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
18.2
The second feature is an OTP factory default setting for V
loaded using the ‘Load factory default’ command. The idea of this feature is to make it unnecessary for the set maker to
specify the V
commands.
18.3
The module maker programming is performed in a special
mode: the calibration mode (CALMM). This mode is
entered via a special interface command, CALMM.
To prevent wrongful programming, a seal bit has been
implemented which prevents the device from entering the
calibration mode. This seal bit, once programmed, cannot
be reversed, thus further changes in programmed values
are not possible. However, it is possible to disable all
programmed values by not applying the ‘Enable OTP’
command.
Applying the programming voltages when not in CALMM
mode will have no effect on the programmed values.
Table 10 Seal bit definition
18.4
The OTP circuitry in the OM6211 contains 14 bits of data:
5 for V
circuitry for 1-bit is called an OTP slice, thus there are
14 OTP slices.
2002 Jan 17
handbook, full pagewidth
48
SEAL BIT
LCD
V
Seal bit
OTP architecture
0
1
PR
84 dot matrix LCD driver
calibration, 8 for V
default value
PR
value. The factory default may be overridden by the set maker in the normal fashion using the ‘Set V
possible to enter calibration mode
calibration mode disabled
OTP V PR default register, 8-bit value
PR
Fig.21 Load V
interface data
default and 1 seal bit. The
ACTION
PR
register: default or specified via interface.
load V PR from an OTP
default register.
load V PR via the interface
PR
29
. This is an 8-bit value from which the V
Each OTP slice consists of 2 main parts: the OTP cell
(a non-volatile memory cell) and the shift register cell
(a flip-flop). The OTP cells are only accessible through
their shift register cells: on the one hand both reading from
and writing to the OTP cells is performed with the shift
register cells, on the other hand only the shift register cells
are visible to the rest of the circuit. The basic OTP
architecture is shown in Fig.22.
This OTP architecture enables the following operations:
1. Reading data from the OTP cells. The content of the
2. Writing data to the OTP cells. Firstly, all 14 bits of data
3. Checking calibration without writing to the OTP cells.
V PR register: 8-bit value
non-volatile OTP cells is transferred to the shift
register where it may affect the OM6211 operation
(provided it has been enabled by the ‘Enable OTP’
command).
are shifted into the shift register via the serial interface.
The content of the shift register is then transferred to
the OTP cells (there are some limitations related to
storing data in these cells, see Section 18.7).
Shifting data into the shift register allows the effects on
the V
LCD
voltage to be observed.
MGU288
Product specification
PR
register can be
OM6211
PR
’