MBM29DL800TA-70 Meet Spansion Inc., MBM29DL800TA-70 Datasheet - Page 27

• Manufacturer Part Number: MBM29DL800TA-70
• Description: Flash Memory Cmos 8m 1m ? 8 / 512k ? 16 Bit
• Manufacturer: Meet Spansion Inc.

Reading Toggle Bits DQ
*1 : Successive reads from the erasing or erase-suspend sector cause DQ
*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ
RY/BY
Ready/Busy
Byte/Word Configuration
Program
Erase
Erase-Suspend Read
(Erase-Suspended Sector)
Erase-Suspend Program
Whenever the system initially begins reading toggle bit status, it must read DQ
to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation.
The system can read array data on DQ
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine
the status of the operation (See “(4) Toggle bit algorithm” in ■FLOW CHART) .
The MBM29DL800TA/BA provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29DL800TA/BA are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to “(8) RY/BY Timing Diagram during Program/Erase
Operations” and “(9) RESET/RY/BY Timing Diagram” in ■TIMING DIAGRAM for a detailed timing diagram. The
RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
be connected to the host system via more than one RY/BY pin in parallel.
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29DL800TA/BA devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
Mode
MB M29DL800TA
6
/DQ
2
Retired Product DS05-20860-7E_August 6, 2007
7
to DQ
Toggle Bit Status Table
5
DQ
DQ
DQ
is high (see “the section on DQ
0
1
0
7
7
7
on the following read cycle.
-70/90
/MBM29DL800BA
Toggle
Toggle
Toggle
DQ
1
2
6
to toggle.
5
5
”) . If it is the system should then
through successive read cycles,
2
7
bit.
to DQ
CC
; multiples of devices may
0
at least twice in a row
Toggle*
Toggle
DQ
1*
1
2
2
1
5
has not
-70/90
0
5
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