MBM29LV400TC-55PF Meet Spansion Inc., MBM29LV400TC-55PF Datasheet - Page 24

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MBM29LV400TC-55PF

Manufacturer Part Number
MBM29LV400TC-55PF
Description
Flash Memory Cmos 4m 512k ? 8/256k ? 16 Bit
Manufacturer
Meet Spansion Inc.
Datasheet
14. Reading Toggle Bits DQ
*1 : Successive reads from the erasing or erase-suspend sector cause DQ
*2 : Reading from non-erase suspend sector address indicates logic “1” at the DQ
15. RY/BY
Ready/Busy
Program
Erase
Erase-Suspend Read
Erase-Suspend Program
(Erase-Suspend Sector)
Furthermore, DQ
mode, DQ
Whenever the system initially begins reading toggle bit status, it must read DQ
to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle
bit after the first read. After the second read, the system would compare the new value of toggle bit with the first.
If the toggle bit is not toggling, this indicates that the device has completed the program or erase operation. The
system can read array data on DQ
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If
it is still toggling, the device did not complete the operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ
mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the
status of operation. (See “4. Toggle Bit Algorithm” in
The MBM29LV400TC/BC provide a RY/BY open-drain output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any read/
write or erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands. If the MBM29LV400TC/BC are placed in an Erase Suspend mode, the RY/BY output will be high.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during the RESET pulse. Refer to “8. RY/BY Timing Diagram during Program/Erase Operations”
and “9. RESET/RY/BY Timing Diagram” in TIMING DIAGRAM for a detailed timing diagram. The RY/BY pin
is pulled high in standby mode.
Since this is an open-drain output, the pull-up resistor needs to be connected to V
be connected to the host system via more than one RY/BY pin in parallel.
2
toggles if this bit is read from an erasing sector.
MBM29LV400TC
2
can also be used to determine which sector is being erased. When the device is in the erase
Mode
6
/DQ
7
2
to DQ
Toggle Bit Status Table
0
5
on the following read cycle.
is high (see “11. DQ
-55/70/90
FLOW CHART.)
DQ
DQ
DQ
/MBM29LV400BC
0
1
7
7
7
5
”) . If it is the system should then determine
5
2
though successive read cycles, deter-
to toggle.
Toggle
Toggle
Toggle
2
DQ
7
bit.
1
to DQ
CC
6
; multiples of devices may
0
at least twice in a row
Toggle*
Toggle
5
DQ
-55/70/90
1*
went high.
1
5
2
2
has not
1
23

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