MBM29LV400TC-55PF Meet Spansion Inc., MBM29LV400TC-55PF Datasheet - Page 25

• Manufacturer Part Number: MBM29LV400TC-55PF
• Description: Flash Memory Cmos 4m 512k ? 8/256k ? 16 Bit
• Manufacturer: Meet Spansion Inc.

24
MBM29LV400TC
16. Byte/Word Configuration
17. Data Protection
18. Low V
19. Write Pulse “Glitch” Protection
20. Logical Inhibit
21. Power-Up Write Inhibit
22. Sector Protection
The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29LV400TC/BC devices. When
this pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
to DQ
becomes the lowest address bit and DQ
an 8-bit operation and hence commands are written at DQ
to “10. Timing Diagram for Word Mode Configuration” and “11. Timing Diagram for Byte Mode Configuration”
and “12. BYTE Timing Diagram for Write Operations” in TIMING DIAGRAM for the timing diagram.
The MBM29LV400TC/BC are designed to offer protection against accidental erasure or programming caused
by spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command
sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
and power-down transitions or system noise.
To avoid initiation of a write cycle during V
than 2.3 V (typically 2.4 V). If V
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the V
to prevent unintentional writes when V
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Writing is inhibited by holding any one of OE = V
must be a logical zero while OE is a logical one.
Power-up of the devices with WE = CE = V
The internal state machine is automatically reset to the read mode on power-up.
Device user is able to protect each sector individually to store and protect data. Protection circuit voids both
program and erase commands that are addressed to protected sectors.
Any commands to program or erase addressed to protected sector are ignored (see “Sector Protection” in
FUNCTIONAL DESCRIPTION) .
CC
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the DQ
level is greater than V
CC
Write Inhibit
LKO
CC
. It is the users responsibility to ensure that the control pins are logically correct
< V
-55/70/90
LKO
, the command register is disabled and all internal program/erase circuits
CC
8
to DQ
is above 2.3 V.
CC
IL
and OE = V
power-up and power-down, a write cycle is locked out for V
/MBM29LV400BC
14
IL
bits are tri-stated. However, the command bus cycle is always
, CE = V
IH
will not accept commands on the rising edge of WE.
0
IH
to DQ
, or WE = V
7
and the DQ
IH
. To initiate a write cycle CE and WE
8
to DQ
-55/70/90
15
bits are ignored. Refer
CC
power-up
15
/A
CC
-1
less
pin
0