MBM30LV0032 Fujitsu Microelectronics, Inc., MBM30LV0032 Datasheet - Page 6

• Manufacturer Part Number: MBM30LV0032
• Description: 32m 4m X 8 Bit Nand-type
• Manufacturer: Fujitsu Microelectronics, Inc.

6
MBM30LV0032
First Cycle
Second Cycle
Third Cycle
SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT
The Program operation is implemented in page units while the Erase operation is carried out in block units.
A
A
(A
* : X = V
0
9
8
to A
to A
is automatically set to “Low” or “High” by the “00h” command or the “01h” command in device inside.)
Memory Cell
Array
7
21
Register
: column address
: page address
IH
or V
IL
I/O0
A
A
A
17
0
9
A
A
13
9
to A
to A
I/O1
A
A
A
512
12
10
18
Figure 1
21
1
528
: block address
: Page address in block
Table 1
16
I/O2
A
A
A
11
19
2
Schematic Cell Layout
Addressing
8 I/O
I/O3
16 pages
A
A
A
12
20
3
I/O7
1 block
I/O0
1) A page consists of (512+16) bytes;
2) A block consists of 16 pages; (8K+256) bytes.
3) Total device density =
I/O4
A
A
A
528 bytes
- 512 bytes for main memory
- 16 bytes for redundancy or other use
13
21
4
Read and Program operation
are executed through Register
Register = 1 page size
16 pages
I/O5
A
A
X*
14
5
512 blocks.
I/O6
A
A
X*
15
6
I/O7
A
X*
A
16
7