MX26L12811MC ETC-unknow, MX26L12811MC Datasheet - Page 14

• Manufacturer Part Number: MX26L12811MC
• Description: 128m [x8/x16] Single 3v Page Mode Mtp Memory
• Manufacturer: ETC-unknow

MX26L12811MC
Set Block Lock-Bit Commands
This device provided the block lock-bits, to lock and
unlock the individual block. To set the block lock-bit, the
two cycle Set Block Lock-Bit command is requested.
This command is invalid while the WSM is running or the
device is suspended. Writing the set block lock-bit com-
mand of 60H followed by confirm command and an ap-
propriate block address. After the command is written,
the device automatically outputs status register data when
read. The CPU can detect the completion of the set lock-
bit event by analyzing the STS pin output or status reg-
ister bit SR.7. Also, reliable operations occur only when
VCC is valid.
Clear Block Lock-Bits Command
All set block lock-bits can clear by the Clear Block Lock-
Bits command. This command is invalid while the WSM
is running or the device is suspended. To Clear the block
lock-bits, two cycle command is requested . The device
automatically outputs status register data when read. The
CPU can detect completion of the clear block lock-bits
event by analyzing status register bit SR.7. If a clear
block lock-bits operation is aborted due to VCC
transitioning out of valid range, block lock-bit values are
left in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit contents
to known values.
VCC--TRANSITIONS
Block erase, program, and lock-bit configuration are not
guaranteed if VCC falls outside of the specified operat-
ing ranges.
The CUI latches commands issued by system software
and is not altered by CE transitions, or WSM actions. Its
state is read array mode upon power-up, after exit from
power-down mode, or after VCC transitions below VLKO.
P/N:PM0990
REV. 1.0, OCT. 29, 2003
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