ZY8105 Power-One, ZY8105 Datasheet - Page 17

• Manufacturer Part Number: ZY8105
• Description: Zy8105 5a Dc-dc Intelligent Pol
• Manufacturer: Power-One

Note
p
defined as percentages of the output voltage.
Therefore, the absolute levels of the thresholds
change when the output voltage setpoint is changed
either by output voltage adjustment or by margining.
In addition, a user can change type of protections
(l
protections. These settings are programmed in the
GUI Fault Management window shown in Figure 30
or directly via the I
shown in Figure 31.
ZD-01740 Rev. 1.0
rotection thresholds and Power Good limits are
atching
Bit 7:5 LR[2:0], Load regulation configuration
Bit 4
Bit 3:0 CLS[3:0], Current limit setting
Bit 7:
Bit
Bit 3:2 OVPL[1:0] : Set Over Voltage Prote
Bit 1:0
R/W-0
LR2
Bit 7
Bit 7
4
---
U
Figure 29. Pro
5
Figure 28. Current Limit Setpoint Register CLS
000: 0 V/A/Ohm
001: 0.39 V/A/Ohm
010: 0.78 V/A/Ohm
011: 1.18 V/A/Ohm
100: 1.57 V/A/Ohm
101: 1.96 V/A/Ohm
110: 2.35 V/A/Ohm
111: 2.75 V/A/Ohm
TCE, Temperature compensation enable
0: disabled
1: enabled
0h: corresponds to 37%
1h: corresponds to 47%
…
Bh: corresponds to 140%
Values higher than Bh are translated to Bh (140%)
Unimplemented
PGLL: Set Power Good Low Level
1 = 95% of Vo
0 = 90% of Vo (Default)
Level
00 = 110% of Vo
01 = 120%
10 = 1
11 = 130% of Vo
UVPL[1:0] : Set Under Volt
00 = 75% of Vo (Default)
01 = 80% of Vo
10 = 85% of Vo
11 = 90% of Vo
that
R/W-0
LR
---
30% of
U
or
1
the
of Vo
Vo (Default)
non-latching)
R/W-0
LR0
---
U
, rea
tection Configuration Register PC2
2
overvoltage
C by writing into the PC1 register
d as ‘
R/W-1
R/W-0
PGLL
TCE
age Protection Level
0’
OVPL1
R/W-1
R/W-1
ction
CLS3
or
and
OVPL0
R/W-0
R/W-0
CLS2
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
R = Readable bit
W = Writable bit
U =
- n = Value at POR
disable
read as ‘0’
Un
read as ‘0’
www.power-one.com
undervol
UVPL1
implemented bit,
R/W-1
R/W-0
CLS1
certain
UVPL0
R/W-1
R/W-0
CLS0
Bit 0
reset
Bit 0
tage
8V to 14V Input
If the non-latching protection is selected, a POL will
attempt to restart every 130ms until the condition
that triggered the protection is removed.
restarting, the output voltages follow tracking and
sequencing settings.
If the latching type is selected, a POL will turn off and
stay off. The POL can be turned on after 130ms, if
the condition that caused the fault is removed and
the respective bit in the ST register was cleared, or
the Turn On command was recycled, or the input
voltage was recycled.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ZY8105 5A DC-DC Intelligent POL
R/W-0
TRE
Bit 7
Figure 31. Protection Configuration Register PC1
TRE: Tracking fault enable
1 = enabled
0 = disabled
PVE: Phase voltage error enable
1 = enabled
0 = disabled
TRP: Tracking fault protection
1 = latching
0 = non latching
OTP: Overtemperature protection configuration
1 = latching
0 = non latching
OCP: Overcurrent protection configuration
1 = latching
0 = non latching
UVP: Undervoltage protection configuration
1 = latching
0 = non latching
OVP: Overvoltage protection configuration
1 = latching
0 = non latching
PVP: Phase Voltage Protection (Not Active)
1 = latching
0 = non latching
R/W-1
Figure 30. Fault Management Window
PVE
R/W-0
TRP
•
R/W-0
OTP
0.5V to 5.5V Output
R/W-0
OCP
Page 17 of 28
R/W-0
UVP
R = Readable bit
W = Writable bit
U = Unimplemented bit,
- n = Value at POR reset
Data Sheet
read as ‘0’
R/W-1
OVP
When
R/W-1
PVP
Bit 0