AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 104

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

AMD-762™ System Controller Data Sheet
Table 34.
92
ST[2:0]
TEST#
DEBUG[2:0]#
PDL_OUTPUT_TEST
DCSTOP#
ROM_SDA
Signal
Signal Descriptions (Continued)
Type
VSS/
VDD
O
O
I
I
I
AGP Status
This bus is used to provide status from the AMD-762™ system controller to the AGP
master. These signals are valid only when the A_GNT# signal is asserted (Low) and must
be ignored by the AGP master at all other times. The status bits are encoded as follow:
000 = Indicates that previously requested low-priority read or flush data is being returned
001 = Indicates that previously requested high-priority read data is being returned to the
010 = Indicates that the master provides low-priority write data for a previous enqueued
011 = Indicates that the master provides high-priority write data for a previous enqueued
100 = Reserved
101 = Reserved
110 = Reserved
111 = Indicates that the master has been given permission to start a bus transaction. The
Test Mode Enable
The TEST# pin is used by AMD for internal chip testing. It is also used to enter NAND tree
and three-state test modes for motherboard manufacturing test, as described in Chapter 3.
Debug
These pins are reserved for general-purpose debug. DEBUG[0]# is used for device scan
testing; the other two pins are reserved. These pins are not used for normal operation but
must be routed to vias on the motherboard to allow test access. The I/O pads for these
signals contain weak pullup resistors, therefore there are no termination requirements on
the motherboard.
Programmable Delay Line Output
This pin provides the output of programmable delay line (PDL) 0 for debug use only. This
pin is not used for normal operation but can be routed to a via on the motherboard to
allow scope access.
DRAM Controller Stop
This pin is used to support ACPI S1 and S3 power management modes. It is asserted by
the AMD-768™ peripheral bus controller or AMD-766™ peripheral bus controller to enter
the S1 power state, and asserted in conjunction with RESET# to enter the S3 state. Refer to
“Power Management” on page 25 for details of AMD-762 system controller power
management modes.
SIP ROM Serial Data
This pin provides the serial data input from an optional serial ROM or microcontroller
when used for loading the SIP parameters for the AMD Athlon processor. This is required
only for cases when SIP parameters are required which are different than those supplied
by the AMD-762 system controller.
to the master.
master.
write command.
write command.
master can enqueue AGP requests by asserting PIPE# or start a PCI transaction by
asserting FRAME#. ST[2:0] are always an output from the core logic and an input to
the master.
Preliminary Information
Miscellaneous Signals
Signal Descriptions
Description
24416C— December 2001
Chapter 7