AMD-762 Advanced Micro Devices, AMD-762 Datasheet - Page 46

• Manufacturer Part Number: AMD-762
• Description: System Controller
• Manufacturer: Advanced Micro Devices

AMD-762™ System Controller Data Sheet
34
The S3 state is exited when the Southbridge detects an enabled
resume event. The Southbridge powers up all of the voltage
planes that are off during the S3 state by asserting PWRON#.
Af t e r a ll of t h e volt a ge pla n e s in t h e syst e m a re wit h i n
sp ecification, and all of the outputs of the system clock
generator are running within specification, PWRGD is asserted
to the Southbridge. The Southbridge then deasserts DCSTOP#
followed by deassertion of PCIRST# (the RESET# pin on the
AMD-762 system controller).
Th e AMD-762 system con t r olle r re t a in s t h e s t a t e of t h e
memory controller configuration registers, which allows BIOS
to immedia t ely access memory to ret r ieve and rest ore the
system context. There are two configuration bits that BIOS uses
to allow the AMD-762 system controlle r to dif f e re n t i a t e
between S3 and all other states following an active to inactive
transition on the RESET# pin. Upon exiting the S3 sleep state,
BIOS writes the appropriate value to these bits, which causes
the AMD-762 syst em controller to exit self-refresh. The two
register bits (STR_Control) are in the DRAM Mode/St at u s
regist er (Dev 0:F0:0x58). Refe r to the AMD-762™ System
Controller Software/BIOS Design Guide, ord e r # 24416 for
detailed information on these bits.
Preliminary Information
Functional Operation
24416C—December 2001
Chapter 2