MSC8122 Freescale Semiconductor, MSC8122 Datasheet - Page 16

• Manufacturer Part Number: MSC8122
• Description: Quad Digital Signal Processor
• Manufacturer: Freescale Semiconductor

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Electrical Characteristics
2.5
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF
load, except where noted otherwise, and a 50 Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1
2.5.2
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3
describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8122 device:
Note:
The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which
raised together. Figure 7 shows a sequence in which
16
System bus
Memory controller
Parallel I/O
Note:
•
•
•
•
PORESET
If possible, bring up the
levels and then the
CLKIN
deassertion to guarantee correct device operation (see Figure 6 and Figure 7).
CLKIN
See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design
recommendations.
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
AC Timings
Output Buffer Impedances
Start-Up Timing
should start toggling at least 16 cycles (starting after
must not be pulled high during
V
V
IL
IH
and
Output Buffers
TRST
V
GND – 0.3 V
GND – 0.7 V
V
DDH
Figure 5. Overshoot/Undershoot Voltage for V
V
DDH
must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15
DDH
V
levels (see Figure 7).
DD
+ 17%
V
+ 8%
GND
DDH
and
Table 6. Output Buffer Impedances
V
DDH
V
levels together. For designs with separate power supplies, bring up the
DDH
V
power-up.
DDH
Must not exceed 10% of clock period
is raised after
CLKIN
V
DDH
can toggle during this period.
V
DD
reaches its nominal level) before
and
CLKIN
Typical Impedance (Ω)
IH
and V
begins to toggle as
50
50
50
IL
Freescale Semiconductor
V
DD
PORESET
V
and
DDH
V
rises.
DDH
V
are
DD