MSC8122 Freescale Semiconductor, MSC8122 Datasheet - Page 45

• Manufacturer Part Number: MSC8122
• Description: Quad Digital Signal Processor
• Manufacturer: Freescale Semiconductor

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7
Table 31
Freescale Semiconductor
Revision
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
provides a revision history for this data sheet.
Revision History
Sep. 2005
Dec. 2007
Nov. 2004
May 2004
Jun. 2004
Sep 2004
Jan. 2005
Apr. 2005
May 2005
May 2005
Oct. 2006
May 2008
Jul. 2005
Jul. 2005
Oct 2005
Apr 2006
Date
• Initial release.
• Updated timing number 32b.
• Updated DSI timing specifications.
• New orderable parts added with other core voltage and temperature options.
• Updated thermal characteristics.
• In Table 2-14, removed references to 30 pF.
• Design guidelines and layout recommendations updated.
• Added 500 MHz core and 166 MHz bus speed options.
• Definitions of GPIO[27–28] updated.
• Bus, TDM, and GPIO timing updated. I
• GPIO[27–28] connections updated. MWBEn replaced with correct name HWBEn.
• Design guidelines update.
• Package type changed to FC-PBGA for all frequencies.
• Low-voltage 300 MHz power changed to 1.1 V.
• HRESET and SRESET definitions updated.
• Undershoot and overshoot values added for V
• RMII timing updated.
• Design guidelines updated and reorganized.
• Added 400 MHz, 1.1 V core part.
• Temperature range descriptions changed to standard and extended.
• CLKOUT timing specifications added.
• Device start-up guidelines added to design considerations and updated power supply guidelines.
• Ordering information updated.
• Multiple AC timing specifications updated.
• Multiple AC timing specifications updated.
• Multiple AC timing specifications updated.
• AC specification table layout modified.
• ETHTX_EN type and TRST description updated.
• Package drawing updated.
• Clock specifications updated.
• Start-up sequence updated.
• V
• V
• Reset timing updated to reflect actual values in Table 2-11.
• Added new timings 17 and 18 for IRQ set time and pulse width in Table 2-13
• Converted to new data sheet format.
• Added PLL supply current to Table 5 in Section 2.4.
• Modified Figure 5 in Section 2.4 to make it clear that the time limits for undershoot referred to values
• Added cross-references between Sections 2.5.2 and Section 3.1 and 3.2.
• Added power-sequence guidelines to Sections 2.5.2.
• Added CLKIN jitter characteristic specifications to
• Added additional guidelines to prevent reverse current to Section 3.1.
• Added connectivity guidelines for DSI in sliding windows mode to Section 3.3.
• Changed V
below –0.3 V and not GND.
MSC8122 Quad Digital Signal Processor Data Sheet, Rev. 15
DDH
DDH
+ 10% changed to V
+20% changed to V
IL
Table 31. Document Revision History
maximum and reference value to 0.8 V in Table 5.
DDH
DDH
+ 17% in Figure 2-1.
+ 8% in Figure 2-1.
2
C timing changed to GPIO timing.
Description
DDH
.
Table
9.
Revision History
45