CD2231 Intel Corporation, CD2231 Datasheet - Page 120
CD2231
Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
1.CD2231.pdf
(178 pages)
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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.4.3.4
120
Register Name: CSR
Register Description: Channel Status
Default Value: x’00
Access: Byte Read/Write
RxEn
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SLIP/MNP 4 Mode
SLIP, MNP4, and Automatic In-Band Flow Control modes are only available on Revision B and
later devices.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 6
0
When clear, the remote station is not requested to stop transmission. RxFloff remains
set until the host issues an STCR command to send an Xon.
RFram – Receive frame status
When set, a frame is being received.
When clear, no frame is being received.
RIdle – Receiver idle status
When set, the receiver input is idle.
When clear, the receiver input is not idle.
Notice that RFram and RIdle are mutually exclusive.
TxEn – Transmitter enabled status
When set, the transmitter is enabled.
When clear, the transmitter is disabled.
TxFloff– Transmit flow off status
This bit has no meaning unless TxIBE in COR2 is set.
When set, an Xoff has been received, and the transmitter has stopped sending data.
When clear, the transmitter is able to transmit if there are characters to send.
TFram – Transmit frame status
When set, a frame is being transmitted.
When clear, no frame is being transmitted.
TIdle – Transmitter idle status
When set, the transmitter output is idle.
When clear, the transmitter output is not idle.
Note that TFram and TIdle are mutually exclusive.
RxEn – Receiver enabled status
When set, the receiver is enabled.
When clear, the receiver is disabled.
Reserved – must be ‘0’.
RFram – Receive frame status
When set, a frame is being received.
When clear, no frame is being received.
RIdle – Receiver idle status
When set, the receiver input is idle.
When clear, the receiver input is not idle.
Note that RFram and RIdle are mutually exclusive.
RFram
Bit 5
Ridle
Bit 4
TxEn
Bit 3
Bit 2
0
Motorola Hex Address: x’1A
TFram
Bit 1
Intel Hex Address: x’19
Datasheet
Tidle
Bit 0
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