CD2231 Intel Corporation, CD2231 Datasheet - Page 123

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
8.5.1.2
8.5.1.3
Datasheet
Register Name: IER
Register Description: Interrupt Enable
Default Value: x’00
Access: Byte Read/Write
Register Name: IER
Register Description: Interrupt Enable
Default Value: x’00
Access: Byte Read/Write
Mdm
Mdm
Bit 7
Bit 7
Interrupt Enable Register (IER), Non-PPP Modes
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Interrupt Enable Register (IER), PPP Mode
Bit 6
Bit 6
0
0
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Modem pin change detect
Master interrupt enable for modem change detect functions. The host can select
which modem pins are monitored for input change and select either or both direc-
tions of change by programming the change detect option bits in COR4 and COR5.
A Group1-type interrupt (see LIVR description) is generated from this enable.
Reserved – must be ‘0’.
RET (Async)
In Asynchronous mode, this bit enables a Group 3 receive exception timeout inter-
rupt when a receive data timeout occurs with an empty receive FIFO. This provides
a mechanism for the host to manage a partially full receive buffer when receive data
stops.
Reserved – must be ‘0’.
Rx data
The receive FIFO threshold has been reached in Interrupt Transfer mode, causing a
Group 3 receive data interrupt. Any receive exception causes a Group 3 receive
exception interrupt.
Timer
General timer(s) timeout
In Synchronous mode, this bit enables a Group 1 interrupt when either timer reaches
zero.
Tx Mpty
Transmitter empty. If enabled, a Group 2 interrupt is generated when the channel is
completely empty of transmit data.
Tx Data
Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer
mode. Group 2 interrupts are generated at the end of transmit DMA buffers or when
the FIFO threshold is reached in Interrupt Transfer mode.
Bit 5
RET
Bit 5
0
Bit 4
Bit 4
0
0
Bit 3
RxD
Bit 3
RxD
TIMER
TIMER
Bit 2
Bit 2
Motorola Hex Address: x’11
Motorola Hex Address: x’11
TxMpty
TxMpty
Bit 1
Bit 1
Intel Hex Address: x’12
Intel Hex Address: x’12
Bit 0
TxD
Bit 0
TxD
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