MB86291A Fujitsu Media Devices Limited, MB86291A Datasheet - Page 5

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MB86291A

Manufacturer Part Number
MB86291A
Description
Graphics Display Controller
Manufacturer
Fujitsu Media Devices Limited
Datasheet

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Note : The host interface can connect the MB86291A to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd.
Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To
TESTH0 to TESTH5
MODE0 to MODE2
Host Interface Pins
DRACK/DMAAK
TEST0, TEST1,
DTACK/TC
Pin Name
D0 to D31
A2 to A24
the V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between.
(Using the SRAM interface allows the MB86291A to use another CPU.) The host CPU is set by the
MODE0 and MODE1 pins as shown below.
use the MODE2 signal at "H" level, set the software setting to two cycles.
RESET
BCLKI
DREQ
WE0
WE1
WE2
WE3
RDY
INT
CS
RD
BS
MODE1 pin
H
H
MODE2 pin
L
L
H
L
Input/output
Input/output
Tristate
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
MODE0 pin
H
H
L
L
Set RDY signal to "Not Ready" level upon completion of bus cycle.
Set RDY signal to "Ready" level upon completion of bus cycle.
Host CPU mode/Ready mode select
Hardware reset
Host CPU bus data
Host CPU bus address (Connect A[24] to MWR in V832 mode.)
Host CPU bus clock
Bus cycle start signal
Chip select signal
Read strobe signal
D0 to D7 write strobe signal
D8 to D15 write strobe signal
D16 to D23 write strobe signal
D24 to D31 write strobe signal
Wait request signal
DMA request signal (active low with both SH and V832)
DMA request acknowledge signal (Connect this to DMAAK in V832 mode.
Active high with both SH and V832.)
DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active
high, V832 = active low)
Host CPU interrupt signal (SH = active low, V832 = active high)
Test signal
(“0” for wait state with SH3; “1” for wait state with SH4, V832, or SPARClite)
SH3
SH4
V832
SPARClite
Ready signal mode
CPU Type
Function
MB86291A
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