MB86291A Fujitsu Media Devices Limited, MB86291A Datasheet - Page 6

• Manufacturer Part Number: MB86291A
• Description: Graphics Display Controller
• Manufacturer: Fujitsu Media Devices Limited

6
MB86291A
Notes :
Notes :
Vide Output Interface
Pin Name
ACOMPR
ACOMPG
ACOMPB
DCLKO
HSYNC
VSYNC
CSYNC
AOUTR
AOUTG
AOUTB
DCLKI
G0-G7
R0-R7
B0-B7
VREF
VRO
EO
GV
The RESET pin requires low level input of at least 300 s after setting “S” (PLL reset signal) to high level.
The host interface transfers data signals at a fixed width of 32 bits.
There are 23 lines for address signals handled in double words (
The external bus can be used at an operating frequency of 100 MHz maximum.
The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level
The host interface supports DMA transfer using an external DMA controller.
The host interface generates a host processor interrupt signal.
Fix the TEST signal at high level.
In the V832 mode, connect the following pins as specified :
The video output interface contains an 8-bit D/A converter to output analog RGB signals. Also, the
eight-bit RGB digital output pins can connect an external digital video encoder.
Using an additional external circuit, the video output interface can generate composite video signals.
The video output interface can provide display synchronized with external video. The mode for
synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set
dot clock as for normal display.
space.
sets the wait state in the SH3 mode. Note that the RDY signal is a tristate output.
Analog output Analog video (R) signal output
Analog output Analog video (G) signal output
Analog output Analog video (B) signal output
Input/output
Input/output
Input/output
SCARLET Pin Name
Analog
Analog
Analog
Analog
Analog
Output
Output
Output
Output
Output
Output
Input
Input
DRACK
DTACK
A24
Display dot clock signal output
Dot clock signal input
Horizontal sync signal output
Horizontal sync signal input in external synchronization mode
Vertical sync signal output
Vertical sync signal input in external synchronization mode
Composite sync signal output
Even/odd-number field identification input
Graphics/video select signal
Digital video (R) signal output
Digital video (G) signal output
Digital video (B) signal output
Reference voltage input pin
R-signal compensation pin
G-signal compensation pin
B-signal compensation pin
Reference current setting pin
Function
V832 Signal Name
32 bits) and 32 Mbytes of address
DMAAK
MWR
TC
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