MB86292 Fujitsu Media Devices Limited, MB86292 Datasheet - Page 5

• Manufacturer Part Number: MB86292
• Description: Graphics Display Controller
• Manufacturer: Fujitsu Media Devices Limited

Note : The host interface can connect the MB86292 to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the
Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To
DTACK/TC
Pin Name
• Host Interface Pins
MODE0-
DRACK/
MODE2
DMAAK
D0-D31
RESET
A2-A24
TESTH
MODE1 pin
BCLKI
DREQ
WE0
WE1
WE2
WE3
RDY
INT
RD
V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between. (Using
the SRAM interface allows the MB86292 to use another CPU.) The host CPU is set by the MODE0 and
MODE1 pins as shown below.
use the MODE2 signal at "H" level, set the software setting to two cycles.
BS
CS
H
H
L
L
MODE2 pin
H
L
Input/output
Input/output
Tristate
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
MODE0 pin
H
H
L
L
Set RDY signal to “Not Ready” level upon completion of bus cycle.
Set RDY signal to “Ready” level upon completion of bus cycle.
Host CPU mode/Ready mode select
Hardware reset
Host CPU bus data
Host CPU bus address (Connect A24 to MWR in V832 mode.)
Host CPU bus clock
Bus cycle start signal
Chip select signal
Read strobe signal
D0-D7 write strobe signal
D8-D15 write strobe signal
D16-D23 write strobe signal
D24-D31 write strobe signal
Wait request signal (“0” for wait state with SH3; “1” for wait state with SH4, V832,
or SPARClite)
DMA request signal (active low with both SH and V832)
DMA request acknowledge signal (Connect this to DMAAK in V832 mode.
Active high with both SH and V832.)
DMA transfer strobe signal (Connect this to TC in V832 mode. SH active high,
V832
Host CPU interrupt signal (SH
Test signal
active low)
SH3
SH4
V832
SPARClite
Ready signal mode
active low, V832
Function
CPU Type
active high)
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MB86292
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