MB86292 Fujitsu Media Devices Limited, MB86292 Datasheet - Page 6

• Manufacturer Part Number: MB86292
• Description: Graphics Display Controller
• Manufacturer: Fujitsu Media Devices Limited

6
MB86292
Notes : The host interface transfers data signals at a fixed width of 32 bits.
Notes : The video output interface outputs RGB pieces of five-bit display data by default. It can output RGB pieces
Pin Name
• Video Output Interface Pins
DCLKO
HSYNC
VSYNC
CSYNC
RGBEN
DCLKI
DISPE
G3-G7
R3-R7
B3-B7
GV
of eight-bit display data depending on conditions. R0-2, G0-2, and B0-2 can be output to MD61-MD63,
MD58-MD60, and MD58-MD60, respectively, by fixing RGBEN to 0. When eight-bit RGB output is selected,
only the 32-bit memory bus width mode can be used.
synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set
dot clock as for normal display.
The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon reset.
The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low level
signal to select video.
Using an additional external circuit, the video output interface can generate composite video signals.
The video output interface can provide display synchronized with external video. The mode for
There are 23 lines for address signals handled in double words (32 bits) and 32 Mbytes of address space.
The external bus can be used at an operating frequency of 100 MHz maximum.
The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level
The host interface supports DMA transfer using an external DMA controller.
The host interface generates a host processor interrupt signal.
The RESET pin requires low level input of at least 300 s after setting "S" (PLL reset signal) to high level.
Fix the TEST signal at high level.
In the V832 mode, connect the following pins as specified :
sets the wait state in the SH3 mode. Note that the RDY signal is a tristate output signal synchronized to the
rise of BCLKI.
Input/output
ORCHID Pin Name
Input/output
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
Input
DRACK
DTACK
A24
Display dot clock signal output
Dot clock signal input
Horizontal sync signal output
Horizontal sync signal input in external synchronization mode
Vertical sync signal output
Vertical sync signal input in external synchronization mode
Composite sync signal output
Display effective period signal
Graphics/video select signal
Digital video (R) signal output
Digital video (G) signal output
Digital video (B) signal output
RGB2-0 output/memory bus (MD63-55) select signal
Function
V832 Signal Name
DMAAK
MWR
TC
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