MB86605 Fujitsu Microelectronics, Inc., MB86605 Datasheet - Page 11

• Manufacturer Part Number: MB86605
• Description: CMOS-wide Scsi-ii Protocol Controller With Pci Interface
• Manufacturer: Fujitsu Microelectronics, Inc.

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4. PCI Bus Interface Mode
26 to 29, 32 to 34, 36,
132, 133, 135, 136,
138, 139, 141, 142,
1, 3 to 5, 7, 9 to 11,
38, 39, 41, 42, 44,
143, 13, 24, 37
46 to 48
Pin no.
Pin no.
130
129
144
126
125
132
125
126
23
14
17
15
20
19
22
PREQ
GNT
AD31 to AD0
C/BE3 to C/BE0 I/O Bus command and Byte Enable signals multiplexed pins.
PAR
TRDY
IRDY
IDSEL
PCLK
SERR
FRAME
STOP
DEVSEL
PERR
DMBHE
(DMUDS)
DMA0
TP
(Transfer
permission)
Pin name
Pin name
OD Address parity error output pin.
I/O
I/O PCI 32-bit address and data multiplexed pins
I/O This is an even parity signal pin for the AD31 to AD0 and C/BE3
I/O This is a frame signal pin that indicates data are transferring on
I/O Data Ready signal of Target side.
I/O Data Ready signal of Initiator (Bus master) side.
I/O This is a stop request signal to stop the data transfer from target
I/O Device select pin. While the device is a target, this pin outputs the
I/O Data parity error input and output pin.
I/O
O
I
I
I
I
I
I
In 80-series mode: This is used to input the BHE signal output by
In 68-series mode: This is used to input the UDS signal output by
This is used to input the address data A0 signal output by the
DMAC in the 80-series mode.
In 68-series mode: Connect to power supply pin (V
This is used to input DMA-transfer-enabling signals.
When the TP signal is active, the SPC performs the DMA transfer.
When this signal becomes inactive during DMA transfer, the
transfer stops temporarily at the block boundary.
This pin is used to request the bus arbiter for use of the bus.
This is the response signal input pin to the REQ signal from the
bus arbiter.
to C/BE0 signals. This PAR signal becomes valid after one clock.
the bus.
to master.
select signal that indicates the self device is selected. While the
device is a master this pin functions as an input pin to indicate
that a device on the bus is selected.
This is a chip select signal that indicates the configuration access.
PCI bus clock input pin. The maximum clock frequency is 33
MHz.
the DMAC when the upper byte of the DMA
data bus is valid.
the DMAC when the upper byte of the DMA
data bus is valid.
Function
Function
MB86605
DD
).
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