MB86605 Fujitsu Microelectronics, Inc., MB86605 Datasheet - Page 50

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MB86605

Manufacturer Part Number
MB86605
Description
CMOS-wide Scsi-ii Protocol Controller With Pci Interface
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
50
MB86605
(7) Target asynchronous output timing (target
* : The value of S varies with the setting condition of the asynchronous set up time register (address 17h).
Note: The output timing regulations are not applicable when the data register is EMPTY in the data phase.
REQ set Low
ACK set Low
REQ set High
Data bus defined
ACK set Low
ACK set High
REQ
ACK
DB7 to 0, P
DB15 to 8, P
*: The time (t
or (t
REQ set High
data bus hold time
ACK set Low
REQ set Low
ACK set High
DIVD
REQ set Low*
Parameter
+ t
DVLD
RACY
).
) of ACK set Low
t
DVLD
t
ROLA
REQ set Low is defined by the longer time either (t
Valid data
t
AROH
initiator)
Symbol
t
t
t
t
t
t
ROLA
AROH
ROHA
DVLD
DIVD
AROL
t
DIVD
t
ROHA
t
S • t
RACY
2 t
Min.
*
CLF
0
0
CLF
– 10
Value
t
DVLD
t
AROH
Valid data
AROL
+ t
Max.
60
40
ROHA
+ t
AROL
)
Unit
ns
ns
ns
ns
ns
ns

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