MB86605 Fujitsu Microelectronics, Inc., MB86605 Datasheet - Page 49

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MB86605

Manufacturer Part Number
MB86605
Description
CMOS-wide Scsi-ii Protocol Controller With Pci Interface
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
(6) Target asynchronous input timing (initiator
* : t
Note: The input timing regulations are not applicable when the data register is FULL in the data phase.
REQ set Low
ACK set Low
REQ set High
Data bus defined
ACK set Low
ACK set High
ACK set Low
RACY
REQ
ACK
DB7 to 0, P
DB15 to 8, P
(ACK set Low
REQ set High
data bus hold time
REQ set Low*
ACK set Low
REQ set Low
ACK set High
ACK set Low
Parameter
REQ set Low) is defined as either longer time of (t
t
ROLA
t
DTSU
t
AROH
target)
Data
Symbol
t
t
t
t
t
t
t
ROLA
AROH
ROHA
DTSU
DHLD
AROL
RACY
t
DHLD
t
t
RACY
ROHA
Min.
10
20
AROH
0
0
+ t
Value
ROHA
+ t
3 t
t
AROL
AROL
CLF
Max.
60
40
+ 40
) or t
MB86605
RACY
itself.
Unit
ns
ns
ns
ns
ns
ns
ns
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