RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 60

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

3.0 Circuit Descriptions
3.5 HDSL Channel
3.5.2 HDSL Receive
Figure 3-22. HDSL Receiver Block Diagram
3-28
3.5.2.1 2B1Q Decoder
BCLKn
QCLKn
RDATn
TDATn
Decoder
2B1Q
State
CNT
The RS8953B contains three identical HDSL receivers, each receiver the same as
the one shown in
destuffing, overhead extraction, descrambling of payload data, error performance
monitoring, and payload mapping of HDSL data from received frames into the
RFIFO. The receive framer monitors incoming HDSL data to locate SYNC words
and to identify frame boundaries for use by other circuits that locate and remove
bit stuffing, to check CRC errors, to extract HOH bits and to map payload data to
the RFIFO. One of the receivers is configured to act as master reference for the
PCM receive channel and from which T1 framing bits are extracted (see
MASTER_SEL, CMD_5; addr 0xE9). The master channel also supplies its 6 ms
frame reference for DPLL clock recovery.
The 2B1Q decoder provides the capability to directly connect to the Conexant
HDSL transceiver. The 2B1Q decoder samples and aligns the incoming sign and
magnitude data. (Refer to
channels operate independent of one another to allow separate, asynchronous
clock signals, to be applied from the system at each HDSL interface.
Table 3-6. 2B1Q Decoder Alignment
PH_LOOP
Detect
SYNC
First Bit
(Sign)
1
1
0
0
Descrambler
STUFF
Detect
Figure
HDSL Framer
Conexant
3-22. The receiver is responsible for frame alignment,
Table 3-6
CRC
CHK
(Magnitudes)
Second Bit
Demux
for 2B1Q mapping.) All three HDSL
0
1
1
0
HOH
HFRAME
Payload
Count
Map
= Command Register Bit
Quaternary Symbol
CHn RSYNC
ROHn
RAUXn
Data to
RFIFO
RS8953B/8953SPB
HDSL Channel Unit
(Quat)
+3
+1
–1
–3
N8953BDSB