RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 89

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

RS8953B/8953SPB
HDSL Channel Unit
RX_ERR_EN
Writing any data value to RFIFO_RST empties the RFIFO and forces the payload mapper to realign HDSL
bytes with respect to the receive HDSL 6 ms frame. The MPU must write RFIFO_RST after modifying the
Receive Payload Map [RMAP; addr 0x64] or the Combination Table [COMBINE_TBL; addr 0xEE] each time
the receive framer changes from the SYNC_ACQUIRED to the IN_SYNC state [STATUS_2; addr 0x06];
whenever a RFIFO error is reported [STATUS_1; addr 0x05]; and after the DPLL has settled. Writing
RFIFO_RST corrupts up to three receive PCM frames worth of data.
Writing any data value to SYNC_RST forces the receive framer to the OUT_OF_SYNC state, which restarts the
SYNC word search and causes the framer to issue an RX_ERR interrupt. The MPU must write SYNC_RST
after modifying FRAMER_EN [RCMD_2; addr 0x61], SYNC_WORD_A, or SYNC_WORD_B. Writing
SYNC_RST to the master HDSL channel corrupts up to three receive PCM frames worth of data and may cause
a DPLL error interrupt.
N8953BDSB
0x62—Receive Elastic Store FIFO Reset (RFIFO_RST)
0x63—Receive Framer Synchronization Reset (SYNC_RST)
Receive Error Interrupt Enable—Receive errors request RX_ERR interrupt and report
RXn_ERR status upon detection of RFIFO errors [STATUS_1; addr 0x05], framer state
transitions or error counter overflows [STATUS_2; addr 0x06]. Disabled channels are
prevented from activating INTR*, or setting RX_ERR [IRR; addr 0x1F]. Receive errors are
always latched in ERR_STATUS [addr 0x3C] regardless of RX_ERR_EN.
0 = Disable RX_ERR interrupts
1 = Enable RX_ERR interrupts
Conexant
4.4 HDSL Receive
4.0 Registers
4-21