RS8953 Conexant Systems, Inc., RS8953 Datasheet - Page 80

• Manufacturer Part Number: RS8953
• Description: High-bit-rate Digital Subscriber Line (hdsl) Channel unit
• Manufacturer: Conexant Systems, Inc.

4.0 Registers
4.2 HDSL Transmit
TFIFO_WL[7:0]
Real-time commands (Bits 0–5) are sampled by the HOH multiplexer on the respective transmit frame to affect
operation in the next outgoing frame. HOH_EN, TWO_LEVEL, and FORCE_ONE command bit combinations
provide the transmit data encoding options needed to perform standard HDSL channel startup procedures.
SCR_EN
TWO_LEVEL
ICRC_ERR
SYNC_SEL
4-12
0x05—Transmit FIFO Water Level (TFIFO_WL)
0x06—Transmit Command Register 1 (TCMD_1)
—
7
7
TX_ERR_EN
6 ms to modify the TZBIT_1 contents for output in next frame. TZBIT_2 through TZBIT_6
are sampled during their respective output times, giving the MPU up to 1 ms after the transmit
frame interrupt to update TZBIT_2; 2 ms to update TZBIT_3; and 5 ms to update TZBIT_6.
This assumes all HDSL transmit frames are output aligned. If differential delay exists between
the transmit channels (as controlled by TFIFO_WL; addr 0x05), then less time is available to
update TZBIT_2–TZBIT_6. Unmodified registers repeatedly output their contents in each
frame. TZBIT[0] is transmitted first.
Transmit FIFO Water Level contains the number of TCLK cycles to delay from the PCM 6 ms
frame to the start of the HDSL transmit SYNC word. A value of zero equals 1 TCLK delay.
Minimum water level values compensate for time to unload one timeslot (8 HDSL bits), time
to load one timeslot (8 PCM bits), the amount of differential delay created by the PCM router
(up to 96 PCM bits in T1 mode), and a phase jitter tolerance (8 to 16 PCM bits). (Refer to
TFIFO_WL description in the PCM Channel Section.)
Scrambler Enable—All transmit HDSL channel bits, except SYNC and STUFF bits, are
scrambled per the SCR_TAP setting in TCMD_2[0x47]. Otherwise, transmit data passes
through the scrambler unchanged.
Two Level Transmit Enable—All 2B1Q encoder magnitude bit outputs are forced to 0 to
comply with standard requirements for a two-level transmit signal.
Inject CRC Error—Logically inverts the six calculated CRC bits in the next frame.
SYNC Word Select—Selects one of two SYNC words, SYNC_WORD_A or
SYNC_WORD_B [addresses 0xCB–0xCC], for transmission in the next frame.
TZBIT_1 is sampled on the respective transmit 6 ms frame interrupt, giving the MPU up to
6
6
FORCE_ONE
5
5
0 = Scrambler bypassed
1 = Scrambler enabled
0 = Four-level 2B1Q encoder operation
1 = Two-level 2B1Q encoder operation
0 = Normal CRC transmission
1 = Transmit errored CRC
0 = SYNC_WORD_A is transmitted
1 = SYNC_WORD_B is transmitted
HOH_EN
4
4
Conexant
TFIFO_WL[7:0]
SYNC_SEL
3
3
ICRC_ERR
2
2
TWO_LEVEL
RS8953B/8953SPB
1
1
HDSL Channel Unit
N8953BDSB
SCR_EN
0
0