CMOS SDRAM Samsung Electronics, CMOS SDRAM Datasheet - Page 4

• Manufacturer Part Number: CMOS SDRAM
• Description: CMOS SDRAM Device Operations
• Manufacturer: Samsung Electronics

DEVICE OPERATIONS
D. DEVICE OPERATIONS (continued)
ADDRESSES of 128Mb
BANK ADDRESSES (BA0 ~ BA1)
: In case x 4
This SDRAM is organized as four independent banks of
8,388,608 words x 4 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
: In case x 8
This SDRAM is organized as four independent banks of
4,194,304 words x 8 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
: In case x 16
This SDRAM is organized as four independent banks of
2,097,152 words x 16 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
ADDRESS INPUTS (A0 ~ A11)
: In case x 4
The 23 address bits are required to decode the 8,388,608 word
locations are multiplexed into 12 address input pins (A
The 12 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
: In case x 8
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 11 address input pins (A
The 12 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
: In case x 16
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 12 address input pins (A
The 12 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
1
1
1
during bank activate command. The 11 bit column addresses
during bank activate command. The 10 bit column addresses
during bank activate command. The 9 bit column addresses
ELECTRONICS
0
0
0
~ BA
~ BA
~ BA
1
1
1
0
0
during read or
during read or
during read or
0
~ BA
~ BA
~ BA
0
0
0
1
1
1
0
0
0
~ A
~ A
~ A
inputs
inputs
inputs
~ BA
~ BA
~ BA
11
11
11
0
0
0
).
).
).
~
~
~
1
1
1
ADDRESSES of 256Mb
: In case x 4
This SDRAM is organized as four independent banks of
16,777,216 words x 4 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
: In case x 8
This SDRAM is organized as four independent banks of
8,388,608 words x 8 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
: In case x 16
This SDRAM is organized as four independent banks of
4,194,304 words x 16 bits memory arrays. The BA
are latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA
are latched at bank active, read, write, mode register set and pre-
charge operations.
ADDRESS INPUTS (A0 ~ A12)
: In case x 4
The 24 address bits are required to decode the 16,777,216 word
locations are multiplexed into 13 address input pins (A
The 13 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
: In case x 8
The 23 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A
The 13 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
: In case x 16
The 22 address bits are required to decode the 4,194,304 word
locations are multiplexed into 13 address input pins (A
The 13 bit row addresses are latched along with RAS and BA
BA
are latched along with CAS, WE and BA
write command.
BANK ADDRESSES (BA0 ~ BA1)
1
1
1
during bank activate command. The 11 bit column addresses
during bank activate command. The 10 bit column addresses
during bank activate command. The 9 bit column addresses
Rev. 0.2 Sep. 1999
CMOS SDRAM
0
~ BA
0
0
~ BA
~ BA
1
during read or
1
1
0
during read or
during read or
0
0
~ BA
~ BA
~ BA
0
~ A
0
0
1
1
1
0
0
0
~ A
~ A
12
inputs
inputs
inputs
~ BA
~ BA
~ BA
).
0
12
12
0
0
~
).
~
).
~
1
1
1