CMOS SDRAM Samsung Electronics, CMOS SDRAM Datasheet - Page 6

• Manufacturer Part Number: CMOS SDRAM
• Description: CMOS SDRAM Device Operations
• Manufacturer: Samsung Electronics

DEVICE OPERATIONS
D. DEVICE OPERATIONS (continued)
BANK ACTIVATE
The bank activate command is used to select a random row in an
idle bank. By asserting low on RAS and CS with desired row and
bank address, a row access is initiated. The read or write opera-
tion can occur after a time delay of t
bank activation. t
therefore it is dependent on operating clock frequency. The mini-
mum number of clock cycles required between bank activate and
read or write command should be calculated by dividing t
with cycle time of the clock and then rounding off the result to the
next higher integer. The SDRAM has four internal banks in the
same chip and shares part of the internal circuitry to reduce chip
area, therefore it restricts the activation of four banks simulta-
neously. Also the noise generated during sensing of each bank of
SDRAM is high, requiring some time for power supplies to recover
before another bank can be sensed reliably. t
the minimum time required between activating different bank. The
number of clock cycles required between different bank activation
must be calculated similar to t
time required for the bank to be active to initiate sensing and
restoring the complete row of dynamic cells is determined by
t
t
active bank can be asserted. The maximum time any bank can be
in the active state is determined by t
cycles for both t
to t
BURST READ
The burst read command is used to access burst of data on con-
secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least t
mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read command
is determined by the mode register which is already programmed.
RAS
RAS
RCD
(min). Every SDRAM bank activate command must satisfy
(min) specification before a precharge command to that
specification.
ELECTRONICS
RAS
RCD
(min) and t
is an internal timing parameter of SDRAM,
RCD
RAS
(min) before the burst read com-
RCD
(max) can be calculated similar
specification. The minimum
RCD
RAS
(max). The number of
(min) from the time of
RRD
(min) specifies
RCD
(min)
The burst read can be initiated on any column address of the
active row. The address wraps around if the initial address does
not start from a boundary such that number of outputs from each
I/O are equal to the burst length programmed in the mode regis-
ter. The output goes into high-impedance at the end of the burst,
unless a new burst read was initiated to keep the data output gap-
less. The burst read can be terminated by issuing another burst
read or burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop command
is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command and is
used to write data into the SDRAM on consecutive clock cycles in
adjacent addresses depending on burst length and burst
sequence. By asserting low on CS, CAS and WE with valid col-
umn address, a write burst is initiated. The data inputs are pro-
vided for the initial address in the same clock cycle as the burst
write command. The input buffer is deselected at the end of the
burst length, even though the internal writing can be completed
yet. The writing can be completed by issuing a burst read and
DQM for blocking data inputs or burst write in the same or another
active bank. The burst stop command is valid at every burst
length. The write burst can also be terminated by using DQM for
blocking data and procreating the bank t
input to be written into the active row. See DQM OPERATION
also.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Pre-
charge all command. Asserting low on CS, RAS, and WE with
high on A
ment, performs precharge on all banks. At the end of t
forming precharge to all the banks, both banks are in idle state.
10
/AP after all banks have satisfied t
Rev. 0.2 Sep. 1999
CMOS SDRAM
RDL
after the last data
RAS
(min) require-
RP
after per-