CMOS SDRAM Samsung Electronics, CMOS SDRAM Datasheet - Page 7

• Manufacturer Part Number: CMOS SDRAM
• Description: CMOS SDRAM Device Operations
• Manufacturer: Samsung Electronics

DEVICE OPERATIONS
D. DEVICE OPERATIONS (continued)
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A
of the bank to be precharged. The precharge command can be
asserted anytime after t
command in the desired bank. t
number of clock cycles required to complete row precharge is cal-
culated by dividing t
the next higher integer. Care should be taken to make sure that
burst write is completed or DQM is used to inhibit writing before
precharge command is asserted. The maximum time any bank
can be active is specified by t
activate command. At the end of precharge, the bank enters the
idle state and is ready to be activated again. Entry to Power down,
Auto refresh, Self refresh and Mode register set etc. is possible
only when all banks are in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
t
latency. The auto precharge command is issued at the same time
as burst read or burst write by asserting high on A
read or burst write by asserting high on A
active until a new command is asserted. Once auto precharge
command is given, no new commands are possible to that partic-
ular bank until the bank achieves idle state.
AUTO REFRESH
The storage cells of 64Mb, 128Mb and 256Mb SDRAM need to be
refreshed every 64ms to maintain data and 16Mb SDRAM need to
be refreshed every 32ms to maintain data. An auto refresh cycle
accomplishes refresh of a single row of storage cells. The internal
counter increments automatically on every auto refresh cycle to
refresh all the rows.
asserting low on CS, RAS and CAS with high on CKE and WE.
The auto refresh command can only be asserted with both banks
being in idle state and the device is not in power down mode
(CKE is high in the previous cycle).
RAS
(min) and "t
ELECTRONICS
RP
" for the programmed burst length and CAS
RP
An auto refresh command is issued by
with clock cycle time and rounding up to
RAS
(min) is satisfied from the bank active
RAS
RP
(max). Therefore, each bank
is defined as the minimum
10
/AP with valid BA
10
/AP, the bank is left
10
/AP. If burst
0
~ BA
1
fied by t
can be calculated by driving t
rounding up to the next higher integer. The auto refresh command
must be followed by NOP's until the auto refresh operation is com-
pleted. All banks will be in the idle state at the end of auto refresh
operation. The auto refresh is the preferred refresh mode when
the SDRAM is being used for normal data transactions. The 16Mb
SDRAM’ s auto refresh cycle can be performed once in 15.6us or a
burst of 2048 auto refresh cycles once in 32ms. The 64Mb and
128Mb SDRAM’ s auto refresh cycle can be performed once in
15.6us or a burst of 4096 auto refresh cycles once in 64ms. The
256Mb SDRAM’ s auto refresh cycle can be performed once in
7.8us or a burst of 8192 auto refresh cycles once in 64ms.
SELF REFRESH
The self refresh is another refresh mode available in the SDRAM.
The self refresh is the preferred refresh mode for data retention
and low power operation of SDRAM. In self refresh mode, the
SDRAM disables the internal clock and all the input buffers except
CKE. The refresh addressing and timing are internally generated
to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE. Once
the self refresh mode is entered, only CKE state being low mat-
ters, all the other inputs including the clock are ignored in order to
remain in the self refresh mode.
The self refresh is exited by restarting the external clock and then
asserting high on CKE. This must be followed by NOP's for a mini-
mum time of t
normal operation. If the system uses burst auto refresh during nor-
mal operation, it is recommended to use burst 8192 auto refresh
cycles for 256Mb and burst 4096 auto refresh cycles for 128Mb/
64Mb and burst 2048 auto refresh cycles for 16Mb immediately
after exiting in self refresh mode.
The time required to complete the auto refresh operation is speci-
RC
(min). The minimum number of clock cycles required
RC
before the SDRAM reaches idle state to begin
RC
with clock cycle time and them
Rev. 0.2 Sep. 1999
CMOS SDRAM