CD016G0PFA Advanced Micro Devices, Inc., CD016G0PFA Datasheet - Page 11

• Manufacturer Part Number: CD016G0PFA
• Description: 16 Megabit(512 K X 32-Bit),CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/write Flash Memory
• Manufacturer: Advanced Micro Devices, Inc.

Pin Configuration
March 22, 2004 S29CD016_00A0
A0–A18
DQ0–DQ31
CE#
OE#
WE#
V
NC
RY/BY#
CLK
ADV#
IND#
WAIT#
WP#
ACC
V
V
RESET#
MCH
SS
IO
CC
(V
CCQ
)
A d v a n c e
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
I n f o r m a t i o n
19-bit address bus for 16 Mb device. A9 supports 12
V autoselect inputs.
32-bit data inputs/outputs/float
Chip Enable Input. This signal is asynchronous
relative to CLK for the burst mode.
Output Enable Input. This signal is asynchronous
relative to CLK for the burst mode.
CLK for the burst mode.
Device ground
Pin not connected internally
V
and commands. When RY/BY# = V
either executing an embedded algorithm or the
device is executing a hardware reset operation.
Clock Input that can be tied to the system or
microprocessor clock and provides the fundamental
timing and internal operating frequency.
Load Burst Address input. Indicates that the valid
address is present on the address inputs.
End of burst indicator for finite bursts only. IND is low
when the last word in the burst sequence is at the
data outputs.
Provides data valid feedback only when the burst
length is set to continuous.
Write Protect input. When WP# = V
outermost bootblock sector in the 75% bank are
write protected regardless of other sector protection
configurations.
Acceleration input. When taken to 12 V, program and
erase operations are accelerated. When not used for
acceleration, ACC = V
Output Buffer Power Supply (1.65 V to 2.75 V, 3.6 V
tolerant)
Chip Power Supply (2.5 V to 2.75 V)
Hardware reset input
Must Connect High (to V
Ready/Busy output and open drain. When RY/BY# =
Write enable. This signal is asynchronous relative to
IH
, the device is ready to accept read operations
S29CD016G
SS
CC
to V
)
CC
.
OL
OL
, the device is
, the two
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