CD016G0PFA Advanced Micro Devices, Inc., CD016G0PFA Datasheet - Page 24

• Manufacturer Part Number: CD016G0PFA
• Description: 16 Megabit(512 K X 32-Bit),CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/write Flash Memory
• Manufacturer: Advanced Micro Devices, Inc.

Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or five clock cycles
24
DQ31-DQ0
DQ31-DQ0
DQ31-DQ0
Addresses
ADV#
CLK
3
4
5
Burst CLK Edge Data Delivery
The device is capable of delivering data on either the rising or falling edge of CLK.
To deliver data on the rising edge of CLK, bit 6 in the Control Register (CR6) is
set to 1. The default configuration is set to the rising edge.
Burst Data Hold Control
The device is capable of holding data for one CLKs. The default configuration is
to hold data for one CLK and is the only valid state.
Asserting RESET# During A Burst Access
If RESET# is asserted low during a burst access, the burst access is immediately
terminated and the device defaults back to asynchronous read mode. Refer to
RESET#: Hardware Reset Pin
CR13
0
0
0
0
0
0
0
0
Valid Address
1st CLK
CR12
0
0
0
0
1
1
1
1
Address 1 Latched
Three CLK Delay
Figure 3. Initial Burst Delay Control
CR11
Table 8. Burst Initial Access Delay
2nd CLK
0
0
1
1
0
0
1
1
Four CLK Delay
Five CLK Delay
A d v a n c e
for more information on the RESET# function.
CR10
0
1
0
1
0
1
0
1
3rd CLK
S29CD016G
D0
I n f o r m a t i o n
4th CLK
Initial Burst Access
D1
(CLK cycles)
D0
OP, OM, OJ
5th CLK
2
3
4
5
6
7
8
9
D2
D1
D0
S29CD016_00A0 March 22, 2004
D2
D3
D1
D2
D4
D3