CMX138 CML Microcircuits, CMX138 Datasheet - Page 28

• Manufacturer Part Number: CMX138
• Description: Audio Scrambler and Sub-Audio Signalling Processor
• Manufacturer: CML Microcircuits

Audio Scrambler and Sub-Audio Signalling Processor
programmed 23- or 24-bit DCS code to be recognised, in the order least significant first through to most
significant DCS code bit last. Table 4 shows a selection of valid 23-bit DCS codes: this does not preclude
other codes being programmed. Recognition of a valid DCS code will be flagged if the decode is
successful (3 or less errors) by setting b10 of the Status register ($C6) to 1. A failure to decode is
indicated by clearing this bit to 0. This bit is updated after the decoding of every 4th bit of the incoming
signal. The actual code received is reported back in the Tone Status register ($CC) according to Table 2,
so that the host µC can determine if it was the true or inverted form of the code.
Once a valid DCS code has been detected, the host µC can route the audio band signal to the AUDIO
output. The audio signal is extracted from the received input signal by band pass filtering, see Figure 6.
The end of DCS transmissions is indicated by a 134.4 ±0.5Hz tone for 150-200ms. When a valid DCS
code has been detected, the CMX138 will automatically scan for the turn-off tone. When the DCS turn-off
tone is detected it will cause a DCS interrupt and report tone 54 (Tone Status b0-7 value 254 decimal);
the receiver audio output can then be muted by the host. Note that, due to the asynchronous nature of the
turn-off tone, it is possible for both a “no-tone” and a “turn-off” tone to be indicated at the end of a DCS
transmission. Note that DCS detection and CTCSS detection can not be performed concurrently.
Notes:
© 2008 CML Microsystems Plc
value
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
True
Reg
1. Register value 84 will select the User Programmable DCS code value in Program Block 2 –
2. Note that the Audio Control register values are shown in decimal.
CTCSS and DCS Setup Register value 184 will select the inverted form of the User
Programmable DCS code.
Invert
value
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Reg
Code
DCS
023
025
026
031
032
043
047
051
054
065
071
072
073
074
114
115
116
125
131
132
134
143
152
155
156
162
165
172
22-12
DCS
7CA
2ED
1EC
6BC
6B7
65D
5B6
0FD
5D1
2E6
35E
72B
7C1
07B
3D3
37A
44D
4A7
31D
763
51F
5F5
6F4
679
693
747
339
05F
bits
DCS
11-0
82C
83C
84C
84D
85C
86D
81A
83A
83B
84E
85A
86A
86E
87A
bits
813
815
816
819
823
827
829
835
839
855
859
863
872
875
value
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
True
Reg
Table 4 DCS 23 Bit Codes
Invert
value
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
Reg
Page 28
Code
DCS
174
205
223
226
243
244
245
251
261
263
265
271
306
311
315
331
343
346
351
364
365
371
411
412
413
423
431
432
22-12
DCS
1FA
43C
0CF
38D
6C6
0EB
79C
6C5
18B
6E9
68E
7B0
45B
58F
5E8
23E
3A9
2F0
3E9
4B9
62F
bits
627
177
794
297
685
158
776
DCS
11-0
8CD
87C
8A3
8A4
8A5
8A9
8B1
8B3
8B5
8B9
8C6
8C9
8D9
8E3
8E6
8E9
8F4
8F5
8F9
90A
90B
91A
885
893
896
909
913
919
bits
value
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
True
Reg
Invert
184
value
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
Reg
Code
DCS
445
464
465
466
503
506
516
532
546
565
606
612
624
627
631
632
654
662
664
703
712
723
731
732
734
743
754
User Defined
D/138_FI1.0/5
22-12
DCS
0BD
0DA
7B8
27E
60B
6E1
3C6
2F8
41B
0E3
19E
0C7
5D9
0F5
01F
7C2
4C3
22B
1E4
10E
14D
20F
671
728
247
393
398
bits
CMX138
DCS
11-0
9AC
9CA
9DA
9DC
9EC
94E
95A
98A
99A
9B2
9B4
9C3
9D3
9D9
9E3
925
934
935
936
943
946
966
975
986
994
997
999
bits