CMX138 CML Microcircuits, CMX138 Datasheet - Page 33

• Manufacturer Part Number: CMX138
• Description: Audio Scrambler and Sub-Audio Signalling Processor
• Manufacturer: CML Microcircuits

Audio Scrambler and Sub-Audio Signalling Processor
7.9.2
A System Clock output, SysClock1 Out, is available to drive additional circuits, as required. This is a
phase locked loop (PLL) clock that can be programmed via the System Clock registers with suitable
values chosen by the user. The System Clock PLL Configure register ($AB) controls the values of the
VCO Output divider and Main Divide registers, while the System Clock Ref. Configure register ($AC)
controls the values of the Reference Divider and signal routing configurations. The PLL is designed for a
reference frequency of 96kHz. If not required, this clock can be independently powersaved. The clock
generation scheme is shown in the block diagram of Figure 15. Note that at power-on the System Clock
output is turned off and the output is held at '0'.
See:
© 2008 CML Microsystems Plc
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o
System Clock Operation
System CLK 1 PLL data - $AB write
System CLK 1 REF - $AC write
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