CMX138 CML Microcircuits, CMX138 Datasheet - Page 42

• Manufacturer Part Number: CMX138
• Description: Audio Scrambler and Sub-Audio Signalling Processor
• Manufacturer: CML Microcircuits

Audio Scrambler and Sub-Audio Signalling Processor
9.1.6
b15-b10
b9-b0
9.1.7
b15,12,11 Clk output divider source
b14
b13
b10-9
b8-b0
Note that on power-up, or after a General Reset, the default settings will not provide a SYSCLK output. To
set SYSCLK to the XTAL frequency it is first necessary to write a '1' to bit 10 of the System CLK 1 PLL
data register ($AB) and also write a '1' to bit 13 of the System CLK 1 REF register ($AC). This will set
SYSCLK to the XTAL frequency and also make the signal available on the SYSCLK pin.
© 2008 CML Microsystems Plc
15
15
Select & PS Clock Sources
VCO Op divide ratio <5-0>
14
14
System CLK 1 PLL data - $AB write
System CLK 1 REF - $AC write
Powersave PLL
Powersave Output Divider
Output Slew Rate
Reference Clk divide value. Divide by 512 is selected by setting these bits to '0'.
Sys CLK 1 Source
Xtal
Sys Clk PLL 1
Main PLL
Test
13
13
divide the selected output clock source by the value in these bits, to generate the System
Clk output. Divide by 64 is selected by setting these bits to '0'.
divide System Clk PLL VCO clock by the value set in these bits as feedback to the PLL
phase detector (PD); when the PLL is stable, this will be the same frequency as the
internal reference as set by b8-b0 of the System Clk Reference and Source Configuration
register ($AC). Divide by 1024 is selected by setting these bits to '0'.
12
12
11
11
b10
0
0
1
1
10
10
op slew
B15
0
1
1
1
b9
0
1
0
1
0 = powersave
0 = powersave / bypass 1 = enabled
9
9
Output Slew Rate
normal
fast
fast
slow
8
8
Page 42
X
1
B12
0
0
7
7
PLL feedback divide ratio <9-0>
6
6
Ref Clock divide ratio <8-0>
1 = enabled
5
5
B11
X
0
1
X
4
4
3
3
2
2
D/138_FI1.0/5
1
1
CMX138
0
0