GS1540-CQR Gennum Corporation, GS1540-CQR Datasheet - Page 12

• Manufacturer Part Number: GS1540-CQR
• Description: Hd-linx (tm) HDTV Serial Digital Non-equalizing Receiver
• Manufacturer: Gennum Corporation

Because most of the PLL circuitry is digital, it is more like
other digital systems which are generally more robust than
their analog counterparts. Additionally, signals like DM/DM
which represent the internal functionality can be generated
without adding additional artifacts. Thus, system debugging
is also possible with these features. The complete slew PLL
is made up of several blocks including the phase detector,
the charge pump and an external Voltage Controlled
Oscillator (VCO).
DIGITAL INPUT BUFFER
The input buffer is a self-biased circuit. On-chip 50Ω
termination resistors provide a seamless interface for other
HD-LINX™ products such as the GS1504 Adaptive Cable
Equalizer.
PHASE DETECTOR
The phase detector portion of the slew PLL used in the
GS1540 is a bi-level digital phase detector. It indicates
whether the data transition occurred before or after with
respect to the falling edge of the internal clock. When the
phase detector is locked, the data transition edges are
aligned to the falling edge of the clock. The input data is
then sampled by the rising edge of the clock, as shown in
Figure 17. In this manner, the allowed input jitter is 1UI p-p
in an ideal situation. However, due to setup and hold time,
the GS1540 typically achieves 0.5UI p-p input jitter
tolerance without causing any errors in this block. When the
signal is locked to the internal clock, the control output from
the phase detector is refreshed at the transition of each
rising edge of the data input. During this time, the phase of
the clock drifts in one direction.
During pathological signals, the amount of jitter that the
phase detector will add can be calculated. By choosing the
proper loop bandwidth, the amount of phase detector
induced jitter can also be limited. Typically, for a 1.41MHz
loop bandwidth at 0.2UI input jitter modulation, the phase
detector induced jitter is about 0.015UIp-p. This is not very
significant, even for the pathological signals.
GENNUM CORPORATION
IN-PHASE CLOCK
INPUT DATA
WITH JITTER
OUTPUT DATA
PHASE ALIGNMENT
Fig. 17 Phase Detector Characteristics
EDGE
RE-TIMING
EDGE
0.5UI
12
CHARGE PUMP
The charge pump in a slew PLL is different from the charge
pump in a linear PLL. There are two main functions of the
charge pump. One function is to hold the frequency
information of the input data. This information is held by
C
capacitor, C
remove common mode noise. Both C
be the same value. The second function of the charge
pump is to provide a binary control voltage to the VCO
depending upon the phase detector output. The output pin,
LFA controls the VCO. Internally there is a 500Ω pull-up
resistor, which is driven with a 100µA current called Ι
Another analog current Ι
proportional to the voltage across the C
same
V
Because of the integrator, Ι
Ι
as often as a clock period. In the locked position, the
average voltage at the LFA (V
that VCO generates frequency ƒ, equal to the data rate
clock frequency. Since Ι
0A and 100µA, there will be two levels generated at the LFA
output.
VCO
The GO1515 is an external hybrid VCO, which has a centre
frequency of 1.485GHz and is also guaranteed to provide
1.485/1.001GHz within the control voltage (3.1V – 4.65V) of
the GS1540 over process, power supply and temperature.
The GO1515 is a very clean frequency source and,
because of the internal high Q resonator, it is an order of
magnitude more immune to external noise as compared to
on-chip VCOs.
The VCO gain, Kƒ, is nominally 16MHz/V. The control
voltage around the average LFA voltage will be 500 x Ι
This will produce two frequencies off from the centre by
ƒ=Kƒ x 500 x Ι
LBCONT
The LBCONT pin is used to adjust the loop bandwidth by
externally changing the internal charge pump current. For
maximum loop bandwidth, connect LBCONT to the most
positive power supply. For medium loop bandwidth,
connect LBCONT through a pull-up resistor (R
low loop bandwidth, leave LBCONT floating. The formula
below shows the loop bandwidth for various configurations.
where LBW nominal is the loop bandwidth when LBCONT is
left floating.
P
LFA_VCC
CP1
could change at the positive edge of the data transition
, which is connected between LFS and LFS. The other
LBW
node.
- 500(Ι
=
CP2
LBW
P
P
/2.
+Ι
The
between LFS and LFA_GND is used to
F
) at any time.
NOMINAL
voltage
P
is changing all the time between
F
F
, with 5mA maximum drive
×
changes very slowly whereas
LFA_VCC
(
----------------------------------------------------- -
(
25kΩ
5kΩ
at
+
+
the
– 500(Ι
R
CP1
R
CP1,
PULL UP
PULL UP
and C
is applied at the
LFA
P
–
/2+Ι
–
PULL-UP
CP2
)
522 - 27 - 02
)
F
node
) is such
should
). For
P
/2.
P
is
.